TSB41BA3IPFP datasheet(47/63 Pages) TI

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TSB41BA3

IEEE 1394b THREEPORT CABLE TRANSCEIVER/ARBITER

SLLS155A − MAY 2003 − REVISED OCTOBER 2003

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION (1394B INTERFACE)

The TSB41BA3 is designed to operate with a LLC such as the Texas Instruments TSB82AA2 when the BMODE

terminal is tied high. Details of operation for the Texas Instruments LLC devices are found in the respective LLC

data sheets. The following paragraphs describe the operation of the PHY-LLC interface. This interface is

formally specified in the IEEE 1394b-2002 standard.

The interface to the LLC consists of the PCLK, LCLK_PMC, CTL0−CTL1, D0−D7, LREQ, PINT, LPS, and

S5_LKON_DS2 terminals on the TSB41BA3, as shown in Figure 22.

S5_LKON_DS2

LPS

PCLK

LREQ

D0–D7

CTL0–CTL1

Link-Layer

Controller

TSB41BA3

LCLK_PMC

PINT

Figure 22. PHY-LLC Interface

The LCLK_PMC terminal provides a clock signal to the PHY. The LLC derives this clock from the PCLK signal

and is phase-locked to the PCLK signal. All LLC to PHY transfers are synchronous to LCLK_PMC.

The PCLK terminal provides a 98.304-MHz interface system clock. All control, data, and PHY interrupt signals

are synchronized to the rising edge of PCLK.

The CTL0 and CTL1 terminals form a bidirectional control bus, which controls the flow of information and data

between the TSB41BA3 and LLC.

The D0−D7 terminals form a bidirectional data bus, which transfers status information, control information, or

packet data between the devices. The TSB41BA3 supports S400B, S200B, and S100B data transfers over the

D0−D7 data bus. In S400B, S200B, and S100B operation all Dn terminals are used.

The LREQ terminal is controlled by the LLC to send serial service requests to the PHY in order to request access

to the serial-bus for packet transmission, read or write PHY registers, or control arbitration acceleration. All data

on LREQ is synchronous to LCLK_PMC.

The LPS and S5_LKON_DS2 terminals are used for power management of the PHY and LLC. The LPS terminal

indicates the power status of the LLC, and may be used to reset the PHY-LLC interface or to disable PCLK. The

S5_LKON_DS2 terminal sends a wake-up notification to the LLC and indicates an interrupt to the LLC when

either LPS is inactive or the PHY register L bit is 0.

The PINT terminal is used by the PHY for the serial transfer of status, interrupt, and other information to the LLC.

TSB41BA3IPFP 数据表(PDF) 47 Page - Texas Instruments

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