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TSB41BA3IPFP 数据表(PDF) 16 Page - Texas Instruments

部件名 TSB41BA3IPFP
功能描述  IEEE1394B THREE PORT CABLE TRANSCEIVER/ARBITER
PDF  63 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

TSB41BA3IPFP 数据表(HTML) 16 Page - Texas Instruments

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TSB41BA3
IEEE 1394b THREEPORT CABLE TRANSCEIVER/ARBITER
SLLS155A − MAY 2003 − REVISED OCTOBER 2003
16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of operating conditions (unless otherwise noted)
(continued)
thermal characteristics
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
RθJA
Junction-to-free-air thermal resistance
Board mounted, No air flow, High conductivity TI
recommended test board, chip soldered or greased to
19.04
°C/W
RθJC Junction-to-case-thermal resistance
recommended test board, chip soldered or greased to
thermal land with 2 oz. copper
0.17
°C/W
RθJA
Junction-to-free-air thermal resistance
Board mounted, No air flow, High conductivity TI
recommended test board with thermal land but no solder
31.52
°C/W
RθJC Junction-to-case-thermal resistance
recommended test board with thermal land but no solder
or grease thermal connection to thermal land with 2 oz.
copper
0.17
°C/W
RθJA
Junction-to-free-air thermal resistance
Board mounted, No air flow, High conductivity JEDEC
49.17
°C/W
RθJC Junction-to-case-thermal resistance
Board mounted, No air flow, High conductivity JEDEC
test board with 1 oz. copper
3.11
°C/W
switching characteristics
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
tr
TP differential rise time, transmit
10% to 90%,
At 1394 connector
0.3
0.8
ns
tf
TP differential fall time, transmit
90% to 10%,
At 1394 connector
0.3
0.8
ns
tsu
Setup time, CTL0, CTL1, D1−D7, LREQ to
PCLK
1394a-2000
50% to 50%,
See Figure 2
2.5
ns
th
Hold time, CTL0, CTL1, D1−D7, LREQ
after PCLK
1394a-2000
50% to 50%,
See Figure 2
0
ns
tsu
Setup time, CTL0, CTL1, D1−D7, LREQ to
LCLK_PMC
1394b
50% to 50%,
See Figure 2
2.5
ns
th
Hold time, CTL0, CTL1, D1−D7, LREQ
after LCLK_PMC
1394b
50% to 50%,
See Figure 2
0
ns
td
Delay time, PCLK to CTL0, CTL1, D1−D7,
PINT
1394a-2000
and 1394b
50% to 50%,
See Figure 3
0.5
7
ns
PARAMETER MEASUREMENT INFORMATION
TPAx+
TPBx+
TPAx−
TPBx−
56
Ω
Figure 1. Test Load Diagram



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