7

LTC3403

3403f

PI FU CTIO S

GDR (Pin 1): MOSFET Gate Driver. Drives a small external

P-channel MOSFET.

to GND, Pin 3, with a 10

µF or greater ceramic capacitor.

GND (Pin 3): Ground Pin.

SW (Pin 4): Switch Node Connection to Inductor. This pin

connects to the drains of the internal main and synchro-

nous power MOSFET switches.

RUN (Pin 5): Run Control Input. Forcing this pin above

1.5V enables the part. Forcing this pin below 0.3V shuts

down the device. In shutdown, all functions are disabled

drawing <1

µA supply current. Do not leave RUN floating.

MODE (Pin 6): Mode Select Input. To select forced con-

Mode operation. Do not leave this pin floating.

REF (Pin 7): External Reference Input. Controls the output

voltage to 3

× the applied voltage at REF. Also turns on the

resistive divider divides the output voltage down by 3 for

comparison to the external reference voltage. The drain of

the P-channel bypass MOSFET is connected to this pin.

Exposed Pad (Pin 9): Connect to GND, Pin 3.

FU CTIO AL DIAGRA

+

–

+

–

+

–

BCMP

EA

P-CHANNEL

FB

+

–

7

5

RUN

OSC

SLOPE

COMP

OSC

FREQ

1.2V

0.85V

0.65V

SLEEP

REF

8

360k

180k

6

MODE

EN

BURST

S

R

RS LATCH

SWITCHING

LOGIC

AND

BLANKING

CIRCUIT

ANTI-

SHOOT-

THRU

Q

Q

5

Ω

2

SW

4

GND

3403 BD

3

9

GDR

1