13

LTC3403

3403f

APPLICATIO S I FOR ATIO

Reductions in power dissipation occur at higher supply

voltages, where the junction temperature is lower due to

may be achieved using an external bypass FET (Figure 5),

which operates in parallel with the network described

above.

Checking Transient Response

The regulator loop response can be checked by looking at

the load transient response. Switching regulators take

several cycles to respond to a step in load current. When

overshoot or ringing that would indicate a stability prob-

lem. For a detailed explanation of switching control loop

theory, see Application Note 76.

A second, more severe transient is caused by switching in

loads with large (>1

µF) supply bypass capacitors. The

discharged bypass capacitors are effectively put in parallel

deliver enough current to prevent this problem if the load

switch resistance is low and it is driven quickly. The only

solution is to limit the rise time of the switch drive so that

Thus, a 10

µF capacitor charging to 3.3V would require a

250

µs rise time, limiting the charging current to about

130mA.

REF

MODE

RUN

1

2

3

4

8

7

6

5

LTC3403

LTC3403 F06

GDR

SW

GND

DAC

BOLD LINES INDICATE HIGH CURRENT PATHS

Figure 6.Layout Diagram

Figure 5. Driving an External Bypass FET

SW

GDR

LTC3403

LTC3403 F05

M1