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LTC6915IGN 数据表(PDF) 12 Page - Linear Technology

部件名 LTC6915IGN
功能描述  Zero Drift, Precision Instrumentation Amplifier with Digitally Programmable Gain
PDF  16 Pages
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制造商  LINER [Linear Technology]
网页  http://www.linear.com
标志 LINER - Linear Technology

LTC6915IGN 数据表(HTML) 12 Page - Linear Technology

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LTC6915
12
6915f
DOUT is always active in serial mode (never tri-stated). This
simplifies the daisy chaining of the multiple devices. DOUT
cannot be “wire-or” to other SPI outputs. In addition, DOUT
does not return to zero at the end of transmission, i.e.
when CS is pulled high.
A LTC6915 may be daisy-chained with other LTC6915s or
other devices having serial interfaces by connecting the
DOUT to the DIN of the next chip while CLK and CS remain
common to all chips in the daisy chain. The serial data is
clocked to all the chips then the CS signal is pulled
high to update all of them simultaneously. Figure 4
shows an example of two LTC6915s in a daisy chained SPI
configuration.
Figure 1. PGA in the Parallel Control Mode
SHDN
IN
IN+
V
HOLD_THRU
CS(D0)
DIN(D1)
CLK(D2)
V+
OUT
SENSE
REF
NC
P/S
DGND
DOUT(D3)
LTC6915
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VOUT
VIN
0.1
µF
PARALLEL GAIN CONTROL CODE = 1010
VOUT = 2
9 V
IN = 512VIN
SHDN
IN
IN+
V
HOLD_THRU
CS(D0)
DIN(D1)
CLK(D2)
V+
OUT
SENSE
REF
NC
P/S
DGND
DOUT(D3)
LTC6915
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VOUT
VIN
0.1
µF
GAIN IS SET BY MICROPROCESSOR. A 10k RESISTOR
ON DOUT(D3) PROTECT THE DEVICE WHEN VD3 > V
+
µP
5V
5V
D0
D1
D2
D3
10k
6915 F01
OPERATIO
Figure 2. Bidirectional Nature of DOUT/D3 Pin
Figure 3. Diagram of Serial Interface
(MSB First Out)
V
V+
DGND
DOUT(D3)
6915 F01
(INTERNAL
NODE)
4-BIT GAIN
CONTROL CODE
4-BIT
LATCH
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
8-BIT
SHIFT-REGISTER
DOUT
(D3)
CLK
DIN
CS
6915 F02



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