LTC6915IGN datasheet(14/16 Pages) LINER

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LTC6915

6915f

Settling Time

The sampling rate is 3kHz and the input sampling period

during which CS is charged to the input differential voltage,

VIN, is approximately 150µs. First assume that on each

input sampling period, CS is charged fully to VIN . Since CS

= CH (= 1000pF), a change in the input will settle to N bits

of accuracy at the op amp noninverting input after N clock

cycles or 333

µs(N). The settling time at the OUT pin is also

affected by the internal op amp. Since the gain bandwidth

of the internal op amp is typically 200kHz, the settling time

is dominated by the switched-capacitor front end for gains

below 100 (see the Low Gain Settling Time vs Settling

Accuracy and the Settling Time vs Gain graphs in the

Typical Performance Characteristics section). In addition,

the worst case settling time after a device-enable (active

low on Pin 1 of a GN package) is equal to the settling due

to the gain plus the input settling time (333

µs • N). For

example, if an LTC6915 is enabled with a logic high on

Pin 1 then, the maximum settling time to 10 bits of

accuracy (0.1%) and a gain equal to 100 is 8.33ms

([333

µs • 1024] + 5ms).

Input Current

Whenever the differential input VIN changes, CH must be

charged up to the new input voltage via CS. This results in

an input charging current during each input sampling

period. Eventually, CH and CS will reach VIN and ideally, the

input current would go to zero for DC inputs.

In reality, there are additional parasitic capacitors which

disturb the charge on CS every cycle even if VIN is a DC

voltage. For example, the parasitic bottom plate capacitor

on CS must be charged from the voltage on the REF pin to

the voltage on the IN– pin every cycle. The resulting input

charging current decays exponentially during each input

sampling period with a time constant equal to RSCS. If the

voltage disturbance due to these currents settles before

the end of the sampling period, there will be no errors due

to source resistance or the source resistance mismatch

between IN+ and IN–. With RS less than 10k, no DC errors

occur due to input current mismatch.

In the Typical Performance Characteristics section of this

data sheet, there are curves showing the additional error

from non-zero source resistance in the inputs. If there

are no large capacitors across the inputs, the amplifier is

less sensitive to source resistance and source resistance

mismatch. When large capacitors are placed across the

OPERATIO

inputs, the input charging currents are placed across the

inputs. The input charging currents described above re-

sult in larger DC errors, especially with source resistor

mismatches.

Power Supply Bypassing

In a dual supply operation, connect a 0.1

µF bypass capaci-

tor from each power supply pin (V+ and V–) to an analog

round plance surrounding an LTC6915. The bypass

capacitor trace to the supply pins must be less than

0.2 inches (an X7R or X5R capacitor type is recom-

mended). In single supply operation, connect the V– pin to

the analog ground plane and bypass the V+ pin.

Shutdown Modes

The IC has two shutdown modes, hardware shutdown and

software shutdown. When SHDN is tied to V+, the IC is in

hardware shutdown mode. During this shutdown mode,

the gain setting digital interface (serial or parallel) and the

main op amp are both disabled, thus the PGA dissipates

very small supply current (see the Electrical Characteristic

table). When SHDN is floating, an internal current source

will pull it down to V–. The digital interface is turned on to

read the gain setting codes. The IC is in normal amplifica-

tion mode as long as the gain control code is other than

0000. If the gain control code is 0000, the IC operates in

software shutdown mode, i.e., the main op amp is turned

off so that the PGA dissipates less power. The DFN

package does not have hardware shutdown.

Setting the Voltage at the REF Pin

The current coming out of the REF pin may affect the

reference voltage at the REF pin (VREF). If VREF is set by a

resistive divider then the VREF voltage is a function of the

VOUT voltage (see Figure 5). In order to minimize the VREF

variations, the total resistance of R1 plus R2 should be

much less than 32k (5k or less) or use a voltage reference

to set VREF.

Figure 5

–

REF

IREF =

VOUT – VREF

32k

VOUT

V+

V–

LTC6915

R = 32k

6915 F05

REF

OUT













–

•(

)

VREF

0.1

µF

OUT

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