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AD8451 数据表(PDF) 21 Page - Analog Devices

部件名 AD8451
功能描述  Low Cost, Precision Analog Front End and Controller for Battery Test/Formation Systems
PDF  33 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD8451 数据表(HTML) 21 Page - Analog Devices

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AD8451
Data Sheet
ISET
+
+
CC LOOP
AMPLIFIER
CV LOOP
AMPLIFIER
IVE1
VVE1
ANALOG
‘NOR’
ISVN
BVP
BVN
GDA
+
+
GIA
ISMEAS
BVMEA
IBAT
IA
DA
V2
R2
C2
VSET
R1
C1
VCTRL
VCLN
VCLP
VINT
BUFFER
V1
VBAT
SENSE
RESISTOR
MODE
5V
+
RS
VINT
POWER
CONVERTER
VINT
IOUT
ISVP
VCTRL
CURRENT
POWER
BUS
MINIMUM
OUTPUT
SELECTOR
V4
V3
V3 < VCTRL < V4
Figure 46. Functional Block Diagram of the CC and CV Loops in Charge Mode (MODE Pin High)
The unity-gain amplifier (VINT buffer) buffers the VINT pins
and drives the VCTRL pin. The VCTRL pin is the control output
of the AD8451 and the control input of the power converter. The
VISET and VVSET voltage sources set the target constant current and
the target constant voltage, respectively. When the CC and CV
feedback loops are in a steady state, the charging current is set at
IBAT_SS =
S
IA
ISET
R
G
V
×
where:
IBAT_SS = is the steady state charging current.
GIA is the IA gain.
RS is the value of the shunt resistor.
The target voltage is set at
VBAT_SS =
DA
VSET
G
V
where:
VBAT_SS = steady state battery voltage.
GDA is the DA gain.
Because the offset voltage of the loop amplifiers is in series with
the target voltage sources, VISET and VVSET, the high precision of
these amplifiers minimizes this source of error.
Figure 47 shows a typical CC/CV charging profile for a Li-Ion
battery. In the first stage of the charging process, the battery is
charged with a CC of 1 A. When the battery voltage reaches a
target voltage of 4.2 V, the charging process transitions such that
the battery is charged with a CV of 4.2 V.
The following steps describe how the AD8451 implements the
CC/CV charging profile (see Figure 46). In this scenario, the
battery begins in the fully discharged state, and the system has
just been turned on such that IBAT = 0 A at Time 0.
1. Because the voltages at the ISMEA and BVMEA pins
are less than the target voltages (VISET and VVSET) at Time 0,
both integrators begin to ramp, increasing the voltage at
the VINT node.
1.25
0
0.25
0.50
0.75
1.00
5
0
1
2
3
4
0
5
4
3
2
1
TIME (Hours)
CC
CHARGE
BEGINS
TRANSITION FROM CC TO CV
CC
CHARGE
ENDS
Figure 47. Representative Constant Current to Constant Voltage Transition
near the End of a Battery Charging Cycle
2. As the voltage at the VINT node increases, the voltage at
the VCRTL node rises, and the output current of the power
converter, IBAT, increases (assuming that an increasing voltage
at the VCRTL node increases the output current of the
power converter).
3. When the IBAT current reaches the CC steady state value,
IBAT_SS, the battery voltage is still less than the target steady
state value, VBAT_SS. Therefore, the CV loop tries to keep
pulling the VINT node up while the CC loop tries to keep
it at its current voltage. At this point, the voltage at the ISMEA
pin equals VISET; therefore, the CC loop stops integrating.
4. Because the loop amplifiers can only pull the VINT node
down due to the analog NOR circuit, the CC loop takes
control of the charging feedback loop, and the CV loop is
disabled.
5. As the charging process continues, the battery voltage
increases until it reaches the steady state value, VBAT_SS, and
the voltage at the BVMEA pin reaches the target voltage, VVSET.
Rev. 0 | Page 20 of 32



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