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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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PSD813F2 数据表(PDF) 82 Page - STMicroelectronics |
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PSD813F2 数据表(HTML) 82 Page - STMicroelectronics |
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82 / 110 page  PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2 82/110 Table 50. CPLD Macrocell Synchronous Clock Mode Timing (3V devices) Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount. 2. CLKIN (PD1) tCLCL = tCH + tCL. Symbol Parameter Conditions -12 -15 -20 PT Aloc Turbo Off Slew rate1 Unit MinMax MinMax MinMax fMAX Maximum Frequency External Feedback 1/(tS+tCO) 22.2 18.8 15.8 MHz Maximum Frequency Internal Feedback (fCNT) 1/(tS+tCO–10) 28.5 23.2 18.8 MHz Maximum Frequency Pipelined Data 1/(tCH+tCL) 40.0 33.3 31.2 MHz tS Input Setup Time 20 25 30 + 4 + 20 ns tH Input Hold Time 0 0 0 ns tCH Clock High Time Clock Input 15 15 16 ns tCL Clock Low Time Clock Input 10 15 16 ns tCO Clock to Output Delay Clock Input 25 28 33 – 6 ns tARD CPLD Array Delay Any macrocell 25 29 33 + 4 ns tMIN Minimum Clock Period2 tCH+tCL 25 29 32 ns |
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