PSD813F2 datasheet(33/110 Pages) STMICROELECTRONICS

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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

PLDS

The PLDs bring programmable logic functionality

to the PSD. After specifying the logic for the PLDs

using the PSDabel tool in PSDsoft Express, the

logic is programmed into the device and available

upon Power-up.

The PSD contains two PLDs: the Decode PLD

(DPLD), and the Complex PLD (CPLD). The PLDs

are briefly discussed in the next few paragraphs,

and in more detail in the section entitled Decode

PLD (DPLD), page 35 and the section entitled

Complex

PLD

(CPLD), page 36.

Figure

13., page 34 shows the configuration of the PLDs.

The DPLD performs address decoding for Select

signals for internal components, such as memory,

registers, and I/O ports.

The CPLD can be used for logic functions, such as

loadable counters and shift registers, state ma-

chines, and encoding and decoding logic. These

logic functions can be constructed using the 16

Output Macrocells (OMC), 24 Input Macrocells

(IMC), and the AND Array. The CPLD can also be

used to generate External Chip Select (ECS0-

ECS2) signals.

The AND Array is used to form product terms.

These product terms are specified using PSDabel.

An Input Bus consisting of 73 signals is connected

to the PLDs. The signals are shown in Table 14.

The Turbo Bit in PSD

The PLDs in the PSD can minimize power con-

sumption by switching off when inputs remain un-

changed for an extended time of about 70ns.

Resetting the Turbo Bit to '0' (Bit 3 of PMMR0) au-

tomatically places the PLDs into standby if no in-

puts are changing. Turning the Turbo mode off

increases propagation delays while reducing pow-

er consumption. See the section entitled POWER

MANAGEMENT, page 62 on how to set the Turbo

Bit.

Additionally, five bits are available in PMMR2 to

block MCU control signals from entering the PLDs.

This reduces power consumption and can be used

only when these MCU control signals are not used

in PLD logic equations.

Each of the two PLDs has unique characteristics

suited for its applications. They are described in

the following sections.

Table 14. DPLD and CPLD Inputs

Note: 1. The address inputs are A19-A4 in 80C51XA mode.

Input Source

Input Name

Number

Signals

MCU Address Bus1

A15-A0

MCU Control Signals

CNTL2-CNTL0

Reset

RST

Power-down

PDN

Port A Input

Macrocells

PA7-PA0

Port B Input

Macrocells

PB7-PB0

Port C Input

Macrocells

PC7-PC0

Port D Inputs

PD2-PD0

Page Register

PGR7-PGR0

Macrocell AB

Feedback

MCELLAB.FB7-

FB0

Macrocell BC

Feedback

MCELLBC.FB7-

FB0

Secondary Flash

memory Program

Status Bit

Ready/Busy

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