AD8341

Rev. 0 | Page 5 of 20

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

18

17

16

15

1

2

3

14

13

DSOP

VPS2

IBBM

IBBP

IFLM

IFLP

4

5

6

VPS2

VPS2

QBBM

QBBP

QFLM

QFLP

AD8341

TOP VIEW

(Not to Scale)

PIN 1

INDICATOR

Figure 2. 24-Lead Lead Frame Chip Scale Package (LFCSP)

Table 3. Pin Function Descriptions

Pin No.

Mnemonic

Function

1, 2

QFLP, QFLM

Q Baseband Input Filter Pins. Connect optional capacitor to reduce Q baseband channel low-pass

corner frequency.

3, 4

QBBP, QBBM

Q Channel Differential Baseband Inputs.

5, 6, 14, 19, 24

VPS2, VPRF

Positive Supply Voltage. 4.75 V − 5.25 V.

7, 8, 11, 12, 20, 23

CMOP, CMRF

Device Common. Connect via lowest possible impedance to external circuit common.

9, 10

RFOP, RFOM

Differential RF Outputs. Must be ac-coupled. Differential impedance 50 Ω nominal.

13

DSOP

Output disable. Pull high to disable output stage.

15, 16

IBBM, IBBP

I Channel Differential Baseband Inputs.

17, 18

IFLM, IFLP

I Baseband Input Filter Pins. Connect optional capacitor to reduce I baseband channel low-pass

corner frequency.

21, 22

RFIM, RFIP

Differential RF Inputs. Must be ac-coupled. Differential impedance 50 Ω nominal.