SL28541

........................ DOC #: SP-AP-0063 (Rev. AA) Page 4 of 31

27

VDD_PLL3_IO

PWR

IO Power supply for PLL3 outputs.

28

SRC2/SATA

O, DIF 100MHz Differential serial reference clocks.

29

SRC2#/SATA#

O, DIF 100MHz Differential serial reference clocks.

30

VSS_SRC

GND

Ground for outputs.

31

SRC3/OE#_0/2_B

I/O,

Dif

100MHz Differential serial reference clocks / 3.3V OE#_0/2_B, input, mappable via

I2C to control either SRC0 or SRC2. (Default SRC3, 100MHz clock)

32

SRC3#OE#_1/4_B

I/O,

Dif

100MHz Differential serial reference clocks / 3.3V OE#_1/4_B input, mappable via

I2C to control either SRC1 or SRC4. (Default SRC3, 100MHz clock)

33

VDD_SRC_IO

PWR

IO power supply for SRC outputs.

34

SRC4

O, DIF 100MHz Differential serial reference clocks.

35

SRC4#

O, DIF 100MHz Differential serial reference clocks.

36

VSS_SRC

GND

Ground for outputs.

37

SRC9

O, DIF 100MHz Differential serial reference clocks.

38

SRC9#

O, DIF 100MHz Differential serial reference clocks.

39

SRC11#/OE#_9

I/O,

Dif

100MHz Differential serial reference clocks/3.3V OE#9 Input controlling SRC9

(Default SRC11, 100MHz clock)

40

SRC11/OE#_10

I/O,

Dif

100MHz Differential serial reference clocks/3.3V OE#10 Input controlling SRC10.

(Default SRC11, 100MHz clock)

41

SRC10

O, DIF 100MHz Differential serial reference clocks.

42

SRC10#

O, DIF 100MHz Differential serial reference clocks.

43

VDD_SRC_IO

PWR

IO Power supply for SRC outputs.

44

CPU_STP#

I

3.3V tolerant input for stopping CPU outputs

45

PCI_STP#

I

3.3V tolerant input for stopping PCI and SRC outputs

46

VDD_SRC

PWR

3.3V Power supply for SRC PLL.

47

SRC6#

O, DIF 100MHz Differential serial reference clocks.

48

SRC6

O, DIF 100MHz Differential serial reference clocks.

49

VSS_SRC

GND

Ground for outputs.

50

SRC7#/OE#_6

I/O,

Dif

100MHz Differential serial reference clocks/3.3V OE#6 Input controlling SRC6.

(Default SRC7, 100MHz clock).

51

SRC7/OE#_8

I/O,

Dif

100MHz Differential serial reference clocks/3.3V OE#8 Input controlling SRC8.

(Default SRC7, 100MHz clock).

52

VDD_SRC_IO

PWR

0.7V power supply for SRC outputs.

53

SRC8#/CPU2#_ITP#

O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 at CKPWRGD

assertion = SRC8

ITP_EN = 1 @ CKPWRGD assertion = CPU2

(Note: CPU2 is an iAMT clock in iAMT mode depending on the configuration set in Byte 11

Bit3:2)

54

SRC8/CPU2_ITP

O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 at CKPWRGD

assertion = SRC8

ITP_EN = 1 @ CKPWRGD assertion = CPU2

(Note: CPU2 is an iAMT clock in iAMT mode depending on the configuration set in Byte 11

Bit3:2)

55

NC

NC

No Connect

56

VDD_CPU_IO

PWR

IO Power supply for CPU outputs.

57

CPU1#

on the configuration set in Byte 11 Bit3:2)

58

CPU1

on the configuration set in Byte 11 Bit3:2)

59

VSS_CPU

GND

Ground for outputs.

Pin No.

Name

Type

Description