SL28541BZCT datasheet(19/31 Pages) SILABS

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SL28541

...................... DOC #: SP-AP-0063 (Rev. AA) Page 19 of 31

PCI_STP# Assertion

The PCI_STP# signal is an active LOW input used for

synchronously stopping and starting the PCI outputs while the

rest of the clock generator continues to function. The set-up

time for capturing PCI_STP# going LOW is 10 ns (tSU). (See

Figure 6.) The PCIF clocks are affected by this pin if their

corresponding control bit in the SMBus register is set to allow

them to be free running.

PCI_STP# Deassertion

The deassertion of the PCI_STP# signal causes all PCI and

stoppable PCIF clocks to resume running in a synchronous

manner within two PCI clock periods, after PCI_STP# transi-

tions to a HIGH level.

CPU_STP#

CPUT

CPUC

CPUT Internal

Tdrive_CPU_STP#,10 ns>200 mV

CPUC Internal

Figure 5. CPU_STP# Deassertion Waveform

Tsu

PC I_STP#

PC I_F

PC I

S RC 100M Hz

Figure 6. PCI_STP# Assertion Waveform

PC I_STP#

PC I_F

PC I

S RC 100 M Hz

Tsu

Td rive _ S R C

Figure 7. PCI_STP# Deassertion Waveform

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