SL28541

........................ DOC #: SP-AP-0063 (Rev. AA) Page 3 of 31

64 QFN Pin Definitions

Pin No.

Name

Type

Description

1

VSS_REF

GND

Ground for outputs.

2

XOUT

O, SE 14.318MHz Crystal output. (Float XOUT if using CLKIN)

3

XIN/CLKIN

I

14.318MHz Crystal input or 3.3V, 14.318MHz input clock signal.

4

VDD_REF

PWR

3.3V Power supply for outputs and also maintains SMBUS registers during

power-down.

5

REF0/FSC/TEST_SEL

I/O

3.3V tolerant input for CPU frequency selection/fixed 14.318MHz clock output.

6

SMB_DATA

I/O

SMBus compatible SDATA.

7

SMB_CLK

I

SMBus compatible SCLOCK.

8

PCI0/OE#_0/2_A

I/O, SE 3.3V, 33MHz clock/3.3V OE# Input mappable via I2C to control either SRC0 or

SRC2. (Default PCI0, 33MHz clock)

9

VDD_PCI

PWR

3.3V Power supply for PCI PLL.

10

PCI1/OE#_1/4_A

I/O, SE 3.3V, 33MHz clock/3.3V OE# Input mappable via I2C to control either SRC1 or

SRC4. (Default PCI1, 33MHz clock)

11

PCI2/TME

I/O, SE 3.3V tolerance input for overclocking enable pin/3.3V, 33MHz clock.

(Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications)

12

PCI3

O, SE, 33 MHz clock.

13

PCI4 / GCLK_SEL

I/O, SE 33 MHz clock output/3.3V-tolerant input for selecting graphic clock source on pin

13, 14, 17and 18

Sampled on CKPWRGD assertion

14

PCIF_0/ITP_EN

I/O, SE 3.3V LVTTL input to enable SRC8 or CPU2_ITP/33 MHz clock output. (sampled

on the CK_PWRGD assertion)

1 = CPU2_ITP, 0 = SRC8

15

VSS_PCI

GND

Ground for outputs.

16

VDD_48

PWR

3.3V Power supply for outputs and PLL.

17

USB_48/FSA

I/O

3.3V tolerant input for CPU frequency selection/fixed 3.3V, 48MHz clock output.

(Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications)

18

VSS_48

GND

Ground for outputs.

19

VDD_IO

PWR

0.7V Power supply for outputs.

20

SRC0/DOT96

O, DIF 100MHz Differential serial reference clocks/Fixed 96MHz clock output.

(Selected via I2C default is SRC0)

21

SRC0#/DOT96#

O, DIF 100MHz Differential serial reference clocks/Fixed 96MHz clock output.

(Selected via I2C default is SRC0)

22

VSS_IO

GND

Ground for PLL2.

23

VDD_PLL3

PWR

3.3V Power supply for PLL3

24

SRC1/LCD100/27_NSS

O, DIF,

SE

True 100 MHz differential serial reference clock output/True 100 MHz LCD video

clock output / Non-spread 27-MHz video clock output.

Selected via GCLK_SEL at CKPWRGD assertion.

25

SRC1#/LCD100#27_SS

O, DIF,

SE

Complementary 100 MHz differential serial reference clock output/Complementary

100 MHz LCD video clock output /Spread 27 MHz video clock output.

Selected via GCLK_SEL at CKPWRGD assertion.

26

VSS_PLL3

GND

Ground for PLL3.

GCLK_SEL

Pin13

Pin14

Pin17

Pin 18

0

DOT96T DOT96C SRC1T/LCD_100T SRC1C/LCD_100C

1

SRCT0

SRCC0

27M_NSS

27M_SS