CYUSB302X datasheet(3/34 Pages) CYPRESS

3 / 34 page

Document Number: 001-55190 Rev. *L

Page 3 of 34

CYUSB302x

Functional Overview

SD3™ is a USB 3.0 SuperSpeed mass-storage controller

providing the latest SD/MMC support. SD3 complies with the SD

Specification, Version 3.0, and the MMC Specification, Version

4.41.

SD3 offers the following access paths among USB and mass

storage ports:

■ A USB-port (U-Port) supporting USB 3.0 peripheral

■ Two mass-storage ports (S0-Port and S1-Port) supporting

mass-storage devices. Following are the possible

configurations for the two mass-storage ports:

❐ SD and MMC

❐ SD and SD

❐ MMC and MMC

❐ SD and SDIO

❐ MMC and SDIO

❐ SDIO and SDIO

Combinations of these accesses can happen independently or

in an interleaved manner.

The SD3 complies with the USB 3.0 v1.0 specification and is also

backward compatible with USB 2.0.

USB Interface (U-Port)

SD3 offers the following features:

■ Supports USB peripheral functionality compliant with the USB

3.0 Specification Revision 1.0 and is backward-compatible with

the USB 2.0 Specification

■ Supports up to 16 IN and 16 OUT endpoints.

■ Supports the USB 3.0 Streams feature. It also supports USB

Attached SCSI (UAS) device class to optimize mass-storage

access performance.

■ As a USB peripheral, SD3 supports UAS and Mass Storage

Class (MSC) peripheral classes.

■ When the USB port is not in use, the PHY and transceiver may

be disabled for power savings.

Figure 1. USB Interface Signals

Mass-Storage Support (S-Port)

The SD3 storage interface port supports the following

specifications:

■ SD Specification, Version 3.0

■ Multimedia Card-System Specification, MMCA Technical

Committee, Version 4.4

■ SDIO Host controller compliant with SDIO Specification

Version 3.00

I2C Interface

SD3 has an I2C interface compatible with the I2C Bus

Specification Revision 3. Because SD3’s I2C interface is capable

of operating only as I2C master, it may be used to communicate

with other I2C slave devices. For example, SD3 may boot from

an EEPROM connected to the I2C interface, as a selectable boot

option.

SD3’s I2C master controller also supports multi-master mode

functionality.

The power supply for the I2C interface is VIO5, which is a

separate power domain from the other serial peripherals. This is

to allow the I2C interface the flexibility to operate at a different

voltage than the other serial interfaces.

The I2C controller supports bus frequencies of 100 kHz,

400 kHz, and 1 MHz. When VIO5 is 1.2 V, the maximum

operating frequency supported is 100 kHz. When VIO5 is 1.8 V,

2.5 V, or 3.3 V, the operating frequencies supported are 400 kHz

and 1 MHz. The I2C controller supports the clock stretching

feature to enable slower devices to exercise flow control.

Both SCL and SDA signals of the I2C interface require external

pull-up resistors. These resistors must be connected to VIO5.

UART Interface

The UART interface of SD3 supports full-duplex communication.

It includes the signals noted in Table 1.

The UART is capable of generating a range of baud rates, from

300 bps to 4608 Kbps, selectable by the firmware. If flow control

is enabled, then SD3's UART only transmits data when the CTS

input is asserted. In addition to this, SD3's UART asserts the RTS

output signal, when it is ready to receive data.

I2S Interface

SD3 has an I2S port to support external audio codec devices.

SD3 functions as I2S Master as transmitter only. The I2S

interface consists of four signals: clock line (I2S_CLK), serial

data line (I2S_SD), word select line (I2S_WS), and master

system clock (I2S_MCLK). SD3 can generate the system clock

as an output on I2S_MCLK or accept an external system clock

input on I2S_MCLK.

The sampling frequencies supported by the I2S interface are

32 kHz, 44.1 kHz, and 48 kHz.

SPI Interface

SD3 supports an SPI Master interface on the Serial Peripherals

port. The maximum operation frequency is 33 MHz.

The SPI controller supports four modes of SPI communication

(see SPI Timing Specification on page 21 for details on the

modes) with the Start-Stop clock. This controller is a

single-master controller with a single automated SSN control. It

supports transaction sizes ranging from 4 bits to 32 bits.

SD3

VBATT

VBUS

SSRX-

SSRX+

SSTX-

SSTX+

D-

D+

Table 1. UART Interface Signals

Signal

Description

Output signal

Input signal

CTS

Flow control

RTS

Flow control

CYUSB302X 数据表(PDF) 3 Page - Cypress Semiconductor

CYUSB302X 数据表(HTML) 3 Page - Cypress Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

数据表下载