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CYUSB302X 数据表(PDF) 20 Page - Cypress Semiconductor |
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CYUSB302X 数据表(HTML) 20 Page - Cypress Semiconductor |
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20 / 34 page ![]() Document Number: 001-55190 Rev. *L Page 20 of 34 CYUSB302x I2S Timing Diagram Figure 5. I2S Transmit Cycle tT tTR tTF tTL tThd tTd tTH SCK SA, WS (output) Table 11. I2S Timing Parameters[5] Parameter Description Min Max Units tT I2S transmitter clock cycle Ttr – ns tTL I2S transmitter cycle LOW period 0.35 Ttr – ns tTH I2S transmitter cycle HIGH period 0.35 Ttr – ns tTR I2S transmitter rise time – 0.15 Ttr ns tTF I2S transmitter fall time – 0.15 Ttr ns tThd I2S transmitter data hold time 0 – ns tTd I2S transmitter delay time – 0.8tT ns Note tT is selectable through clock gears. Max Ttr is designed for 96-kHz codec at 32 bits to be 326 ns (3.072 MHz). Note 5. All parameters guaranteed by design and validated through characterization. |
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