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AD5246

ELECTRICAL CHARACTERISTICS—5 kΩ VERSION

Table 1. VDD = 5 V ±10% or 3 V ± 10%; VA = +VDD; –40°C < TA < +125°C; unless otherwise noted

Parameter

Symbol

Conditions

Min

Typ1

Max

Unit

DC CHARACTERISTICS—RHEOSTAT MODE

Resistor Differential Nonlinearity2

R-DNL

RWB

–1.5

±0.1

+1.5

LSB

Resistor Integral Nonlinearity2

R-INL

RWB

–4

±0.75

LSB

Nominal Resistor Tolerance3

∆RAB

TA = 25°C

–30

+30

Resistance Temperature Coefficient

∆RAB/∆T

Wiper = No Connect

ppm/°C

RWB

Code=0x00, VDD = 5 V

150

Ω

Code=0x00, VDD = 2.7 V

150

400

Ω

RESISTOR TERMINALS

Voltage Range4

VB, W

GND

VDD

Capacitance5 B

f = 1 MHz, Measured to GND, Code = 0x40

Capacitance5 W

f = 1 MHz, Measured to GND, Code = 0x40

Common-Mode Leakage

ICM

DIGITAL INPUTS AND OUTPUTS

Input Logic High

VIH

VDD = 5 V

2.4

Input Logic Low

VIL

VDD = 5 V

0.8

Input Logic High

VIH

VDD = 3 V

2.1

Input Logic Low

VIL

VDD = 3 V

0.6

Input Current

IIL

VIN = 0 V or 5 V

±1

µA

Input Capacitance5

CIL

POWER SUPPLIES

Power Supply Range

VDD RANGE

2.7

5.5

Supply Current

IDD

VIH = 5 V or VIL = 0 V

µA

Power Dissipation6

PDISS

VIH = 5 V or VIL = 0 V, VDD = 5 V

µW

Power Supply Sensitivity

PSSR

VDD = +5 V ± 10%, Code = Midscale

±0.01

±0.02

%/%

DYNAMIC CHARACTERISTICS5, 7

Bandwidth –3 dB

BW_5K

RAB = 5 kΩ, Code = 0x40

1.2

MHz

Total Harmonic Distortion

THDW

VA = 1 V rms, VB = 0 V, f = 1 kHz

0.05

VW Settling Time

VA = 5 V, ±1 LSB Error Band

µs

Resistor Noise Voltage Density

eN_WB

RWB = 2.5 kΩ, RS = 0 Ω

nV/√Hz

1 Typical specifications represent average readings at 25°C and VDD = 5 V.

2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.

3 Code = 0x7F.

4 Resistor terminals A and W have no limitations on polarity with respect to each other.

5 Guaranteed by design and not subject to production test.

6 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

7 All dynamic characteristics use VDD = 5 V.

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