AD5246

The first byte of the AD5246 is a slave address byte (see

and

). It has a 7-bit slave address and a R/W bit. The

seven MSBs of the slave address are 0101110 followed by 0 for a

write command or 1 to place the device in read mode.

Table 5

able 5

Table 6

1.

The master initiates data transfer by establishing a START

condition, which is when a high-to-low transition on the

SDA line occurs while SCL is high (see

). The

following byte is the slave address byte, which consists of

the 7-bit slave address followed by an R/W bit (this bit

determines whether data will be read from or written to

the slave device).

Figure 26

Figure 26

The slave whose address corresponds to the transmitted

address responds by pulling the SDA line low during the

ninth clock pulse (this is termed the acknowledge bit). At

this stage, all other devices on the bus remain idle while the

selected device waits for data to be written to or read from

its serial register. If the R/W bit is high, the master will read

from the slave device. On the other hand, if the R/W bit is

low, the master will write to the slave device.

2.

In write mode, after acknowledgement of the slave address

byte, the next byte is the data byte. Data is transmitted over

the serial bus in sequences of nine clock pulses (eight data

bits followed by an acknowledge bit). The transitions on

the SDA line must occur during the low period of SCL and

remain stable during the high period of SCL (see T

).

3.

In read mode, after acknowledgment of the slave address

byte, data is received over the serial bus in sequences of

nine clock pulses (a slight difference from the write mode

where eight data bits are followed by an acknowledge bit).

Similarly, the transitions on the SDA line must occur

during the low period of SCL and remain stable during the

high period of SCL (see

).

Figure 27

Figure 27

4.

When all data bits have been read or written, a STOP

condition is established by the master. A STOP condition is

defined as a low-to-high transition on the SDA line while

SCL is high. In write mode, the master will pull the SDA

line high during the tenth clock pulse to establish a STOP

condition (see

). In read mode, the master will

issue a No Acknowledge for the ninth clock pulse (i.e., the

SDA line remains high). The master will then bring the

SDA line low before the tenth clock pulse, which goes high

to establish a STOP condition (see

).

A repeated write function gives the user flexibility to update the

RDAC output a number of times after addressing the part only

once. For example, after the RDAC has acknowledged its slave

address in write mode, the RDAC output will update on each

successive byte. If different instructions are needed, write/read

mode has to start again with a new slave address and data byte.

Similarly, a repeated read function of the RDAC is also allowed.

LEVEL SHIFTING FOR BIDIRECTIONAL INTERFACE

While most legacy systems may be operated at one voltage, a

new component may be optimized at another. When two

systems operate the same signal at two different voltages, proper

level shifting is needed. For instance, one can use a 3.3 V

shifting scheme is needed to enable a bidirectional communi-

cation so that the setting of the digital potentiometer can be

shows one

of the implementations. M1 and M2 can be any N channel

threshold FETs such as the FDV301N.

igure 29

Figure 29. Level Shifting for Operation at Different Potentials

AD5246

SDA1

SCL1

D

G

3.3V

5V

S

M1

SCL2

SDA2

G

S

M2

D

ESD PROTECTION

All digital inputs are protected with a series input resistor and

parallel Zener ESD structures shown in F

and

.

This applies to the digital input pins SDA and SCL.

igure 30

Figure 30. ESD Protection of Digital Pins

Figure 31

Figure 31. ESD Protection of Resistor Terminals

LOGIC

340

Ω

GND

B,W

GND

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