MB91F525FHDPMC datasheet(132/280 Pages) CYPRESS

132 / 280 page

Document Number: 002-04662 Rev. *F

Page 132 of 280

MB91520 Series

Interrupt Factor

Interrupt Number

Interrupt

Level

Offset

Default

Address for

TBR

Decimal Hexa Decimal

32-bit ICU5 (fetching/measurement)

ICR41

318H

000FFF18H

A/D converter

32/33/34/35/36/37/38/39/40/41/42/43/44/45/46/

32-bit OCU 6/7/10/11 (match)

ICR42

314H

000FFF14H

32-bit OCU 8/9 (match)

ICR43

310H

000FFF10H

Base timer 0 IRQ0

ICR44

30CH

000FFF0CH

Base timer 0 IRQ1

Base timer 1 IRQ0

ICR45

308H

000FFF08H

Base timer 1 IRQ1

DMAC 0/1/2/3/4/5/6/7/8/9/10/11/12/13/14/15

ICR46

304H

000FFF04H

Delay interrupt

ICR47

300H

000FFF00H

System reserved

(Used for REALOS)

2FCH 000FFEFCH

System reserved

(Used for REALOS)

2F8H

000FFEF8H

Used with the INT instruction

255

2F4H

000H

000FFEF4H

000FFC00H

Note: It does not support a DMA transfer request caused by an interrupt generated from a peripheral to which no

RN (Resource Number) is assigned.

*1: It does not support a DMA transfer by the status of the multi-function serial interface and I2C reception.

*2: Reload timer ch.4 to ch.7 do not support a DMA transfer by the interrupt.

*3: PPG ch.24 to ch.47 do not support a DMA transfer by the interrupt.

*4: The clock calibration unit does not support a DMA transfer by the interrupt.

*5: 32-bit Free-run timer ch.3, ch.4 and ch.5 do not support a DMA transfer by the interrupt.

*6: There is no resource corresponding to the interrupt level.

*7: It does not support a DMA transfer by the external low-voltage detection interrupt.

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