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MB91F525FHDPMC 数据表(PDF) 152 Page - Cypress Semiconductor

部件名 MB91F525FHDPMC
功能描述  32-bit FR81S Microcontroller
PDF  280 Pages
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制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
标志 CYPRESS - Cypress Semiconductor

MB91F525FHDPMC 数据表(HTML) 152 Page - Cypress Semiconductor

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Document Number: 002-04662 Rev. *F
Page 152 of 280
MB91520 Series
(4-1-2) Bit setting: SMR: MD2 = 0, SMR: MD1 = 1, SMR : MD0 = 0, SMR: SCINV = 1, SCR:SPI = 0
(TA: -40 °C to +125 °C, VCC = AVCC = 5.0 V ± 10 %/VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V)
Parameter
Symbol
Pin Name
Conditions
Value
Unit
Remarks
Min
Max
Serial clock cycle
time
tSCYC
SCK0 to SCK11
-
4tCPP
-
ns
Internal
shift
clock
mode
output pin :
CL = 50 pF
SCK
↑ →
SOT delay time
tSHOVI
SCK0 to SCK2,
SCK5 to SCK11
SOT0 to SOT2,
SOT5 to SOT11
-30
30
ns
SCK3 , SCK4
SOT3 , SOT4
-300
300
ns
Valid SIN
→
SCK
↓ setup time
tIVSLI
SCK0 to SCK2,
SCK5 to SCK11
SIN0 to SIN2,
SIN5 to SIN11
34
-
ns
SCK3 , SCK4
SIN3, SIN4
300
-
ns
SCK
↓ →
Valid SIN hold time
tSLIXI
SCK0 to SCK11
SIN0 to SIN11
0
-
ns
Serial clock
"H"pulse width
tSHSL
SCK0 to SCK11
-
tCPP+10
-
ns
External
shift
clock
mode
output pin:
CL = 50 pF
Serial clock
"L" pulse width
tSLSH
2tCPP-10
-
ns
SCK
↑ →
SOT delay time
tSHOVE
SCK0 to SCK2,
SCK5 to SCK11
SOT0 to SOT2,
SOT5 to SOT11
-
33
ns
SCK3 , SCK4
SOT3 , SOT4
-
300
ns
Valid SIN
→
SCK
↓ setup time
tIVSLE
SCK0 to SCK11
SIN0 to SIN11
10
-
ns
SCK
↓ →
Valid SIN hold time
tSLIXE
20
-
ns
SCK fall time
tF
SCK0 to SCK11
-
5
ns
SCK rise time
tR
SCK0 to SCK11
-
5
ns
Notes:
AC characteristic in CLK synchronized mode.
CL is the load capacitance applied to pins during testing.
The maximum bard rate is limited by internal operation clock used and other parameters. Please use ch.3 and ch.4 with maximum
baud rate 400 kbps or less.
See Hardware Manual for details.



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