| 数据搜索系统,热门电子元器件搜索 |
|
MB91F525FHDPMC 数据表(PDF) 226 Page - Cypress Semiconductor |
|
|
|||||||||||||||||||||||||||||
MB91F525FHDPMC 数据表(HTML) 226 Page - Cypress Semiconductor |
|
226 / 280 page ![]() Document Number: 002-04662 Rev. *F Page 226 of 280 MB91520 Series ■ Scope of Impact For the affected parts, when the Power-On Reset and Internal Low Voltage Detection are not generated, the MCU may set invalid package and sub clock option information. Therefore, the MCU may operate with an invalid pin configuration. ■ Workaround For the affected parts, it is necessary to satisfy at least one of the Power-On Reset requirements for any Power-On event as given below: (1) The VCC voltage is less than 200 mV for 50 ms or longer (tOFF) (2) VCC Power ramp rate is less than 4 mV/µs (dV/dt) until a voltage level for a safe Power-On detection is reached (3) C-pin voltage is below 60 mV when VCC is turned on again If the customer system does not satisfy the condition above-mentioned, Cypress will releases new version D, so Cypress recommends the version D for MB91F52x. The new version prevents the limitation when an external reset signal is asserted at pin RSTX anytime the supply voltage (VCC) is turned on. ■ Fix Status Will be fixed in production silicon version D, E 2. Limitation for Watch mode (power off) ■ Problem Definition If the below all trigger conditions (1) to (3) are satisfied, the below registers will be initialized after MCU recovers from watch mode (power off). ■ Trigger Conditions (1) Using the watch mode (power off) (2) Interrupt levels that are used as sources for recovering from the watch mode (power off) are ‘16’ to ‘30’, or using NMIX pin as source for recovering from the watch mode (power off) (3) The sources for recovering from the watch mode (power off) are generated between PCLK 1 cycle and PMUCLK 3 cycles (*), after CPU state changes to the watch mode (power off) (*): In case of PCLK = 0.5 MHz and PMUCLK = 32 kHz, it is approx. 2 µs to 100 µs ■ Scope of Impact If the all trigger conditions (1) to (3) are satisfied, the below registers will be initialized after MCU recovers from watch mode (power off). WTCRH, WTCRM, WTCRL CSELR.SCEN CMONR.SCRDY CCRTSELR.CST CCRTSELR.CSC |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |