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MB91F525FHDPMC 数据表(PDF) 226 Page - Cypress Semiconductor

部件名 MB91F525FHDPMC
功能描述  32-bit FR81S Microcontroller
PDF  280 Pages
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制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
标志 CYPRESS - Cypress Semiconductor

MB91F525FHDPMC 数据表(HTML) 226 Page - Cypress Semiconductor

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Document Number: 002-04662 Rev. *F
Page 226 of 280
MB91520 Series
■ Scope of Impact
For the affected parts, when the Power-On Reset and Internal Low Voltage Detection are not generated, the MCU may
set invalid package and sub clock option information. Therefore, the MCU may operate with an invalid pin configuration.
■ Workaround
For the affected parts, it is necessary to satisfy at least one of the Power-On Reset requirements for any Power-On event
as given below:
(1) The VCC voltage is less than 200 mV for 50 ms or longer (tOFF)
(2) VCC Power ramp rate is less than 4 mV/µs (dV/dt) until a voltage level for a safe Power-On detection is reached
(3) C-pin voltage is below 60 mV when VCC is turned on again
If the customer system does not satisfy the condition above-mentioned, Cypress will releases new version D, so Cypress
recommends the version D for MB91F52x. The new version prevents the limitation when an external reset signal is
asserted at pin RSTX anytime the supply voltage (VCC) is turned on.
■ Fix Status
Will be fixed in production silicon version D, E
2.
Limitation for Watch mode (power off)
■ Problem Definition
If the below all trigger conditions (1) to (3) are satisfied, the below registers will be initialized after MCU recovers from
watch mode (power off).
■ Trigger Conditions
(1) Using the watch mode (power off)
(2) Interrupt levels that are used as sources for recovering from the watch mode (power off) are
‘16’ to ‘30’, or using
NMIX pin as source for recovering from the watch mode (power off)
(3) The sources for recovering from the watch mode (power off) are generated between PCLK 1 cycle and PMUCLK
3 cycles (*), after CPU state changes to the watch mode (power off)
(*): In case of PCLK = 0.5 MHz and PMUCLK = 32 kHz, it is approx. 2 µs to 100 µs
■ Scope of Impact
If the all trigger conditions (1) to (3) are satisfied, the below registers will be initialized after MCU recovers from watch
mode (power off).
WTCRH, WTCRM, WTCRL
CSELR.SCEN
CMONR.SCRDY
CCRTSELR.CST
CCRTSELR.CSC



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