AC101L-DS06-R datasheet(16/54 Pages) BOARDCOM

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AC101L

Preliminary Data Sheet

8/9/04

B roa dcom Co rpo rat ion

Page 6

MAC Interface

Document

AC101L-DS06-R

MAC INTERFACE

MII

The Media Independent Interface (MII) is an 18-wire MAC/PHY interface described in IEEE 802.3u. The purpose of the

interface is to allow MAC layer devices to attach to a variety of physical layer devices through a common interface. MII

operates at either 100 Mbps or 10 Mbps, depending on the speed of the physical layer. With clocks running at either 25 MHz

or 2.5 MHz, 4-bit data are clocked between the MAC and PHY, synchronously with Enable and Error signals.

At the time of PLL lock on an incoming signal from the wire interface, the PHY generates RX_CLK at either 2.5 MHz for

10 Mbps or 25 MHz for 100 Mbps.

On receipt of valid data from the wire interface, RXDV goes active signaling the MAC that valid data will be presented on the

RXD[3:0] pins at the speed of the RX_CLK.

On transmission of data from the MAC, TXEN is presented to the PHY, indicating the presence of valid data on TXD[3:0].

TXD[3:0] are sampled by the PHY( synchronous to TX_CLK) during the time that TXEN is valid.

SMI

The PHYs internal registers are accessible only through the MII 2-wire Serial Management Interface (SMI). MDC is a clock

input to the PHY, which is used to latch in or out data and instructions for the PHY. The clock can run at any speed from DC

to 25 MHz. MDIO is a bidirectional connection used to write instructions to, write data to, or read data from the PHY. Each

data bit is latched either in or out on the rising edge of the MDC. The MDC is not required to maintain any speed or duty

cycle, provided no half cycle is less than 20 ns, and that data are presented synchronous to the MDC.

MDC/MDIO are a common signal pair to all PHYs on a design. Therefore, each PHY needs to have its own unique physical

address. The physical address of the PHY is set using the pins defined as PHYAD[4:0]. These input signals are strapped

externally, and are sampled as reset is negated. At idle, the PHY is responsible to pull the MDIO line to a high state.

Therefore, a 1 k

Ω resistor is required to connect the MDIO line to VCC.

PHYSICAL LAYER INTERFACES

The two supported interfaces are the twisted-pair (TP) interface with auto-MDI/MDIX selection, and the fiber-optic Interface

with PECL signaling.

The selection of these two interfaces is performed at reset time by the SD/FXEN signal (pin 28). Pull pin 28 LOW to enable

the TP interface, or connect pin 28 to the fiber module to enable FX interface.

AC101L-DS06-R 数据表(PDF) 16 Page - Broadcom Corporation.

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