AC101L-DS06-R datasheet(18/54 Pages) BOARDCOM

18 / 54 page

AC101L

Preliminary Data Sheet

8/9/04

B roa dcom Co rpo rat ion

Page 8

Pin Descriptions

Document

AC101L-DS06-R

BURNIN/

LED0

BURNIN: Resets read input. Set Active LOW to put the chip in burn-in test mode.

LED0 (output): active LOW, the default behavior is ON when the chip is in link-up condition, and is BLINK when the chip

detects transmit or receive activity.

SPD100/

LED1

SPD100: Resets read input.

If ANEN is Low, SPD100 sets the TP port speed in register 0.

If ANEN is High, SPD100 is used to set 100 Mbps half-duplex and 100 Mbps full-duplex bits in register 4.

LED1 (output): active LOW. The default behavior is ON when the chip is operating at 100 Mbps and is OFF when the chip

is operating at 10 Mbps.

DUPLEX/

LED2

DUPLEX: Resets read input.

If ANEN is Low, DUPLEX sets the TP port in full-duplex mode in register 0.

If ANEN is High, DUPLEX is used to set 10 Mbps FDX and 100 Mbps FDX bits in register 4.

LED2 (output): active LOW. The default behavior is ON when the chip is operating in full-duplex mode and is OFF when

the chip is operating in half-duplex mode.

ANEN/LED3

ANEN (resets read input): Auto-negotiation enable for the twisted-pair port. Pull high to enable auto-negotiation. Pull low to

disable auto-negotiation.

LED3 (output): active LOW. The default behavior is BLINK when the chip detect collision is in half-duplex mode.

PDOWN

PDOWN (input): Power-down input. This pin must be pulled high externally for normal operation. Pulling this pin low puts

both the TP and fiber port into power-down mode. This is a regular input, not a reset read signal.

VCC

+2.5V power supply.

RXN

Receive. For TP port in MDI mode.

Transmit. For TP port in MDIX mode.

RXP

Receive +. For TP port in MDI mode.

Transmit +. For TP port in MDIX mode.

SD/FXEN

SD/FXEN (analog input): This pin must be pulled low externally for normal TP mode.

Connect to fiber module to enable FX mode; also serves as signal detect input.

GND

Ground.

GND

Ground.

RBIAD

Bias resistor connection. Connect to a 10K 1% resistor to GND.

VCCPLL

+2.5V supply for analog bias, PLL modules.

GND

Ground.

TXN

Transmit. In MDI mode.

Receive. In MDIX mode.

TXP

Transmit +. In MDI mode.

Receive +. In MDIX mode.

VCC25OUT

+2.5VCC out from the on-chip regulator.

GND

Ground.

GND

Ground.

XTAL output.

XTAL input.

In MII Mode: XI and XO is designed to connect to a 25 MHz., 50 PPM XTAL or 25 MHz OSC.

VCC33IN

3.3V Power supply input.

RST

I U

Reset input. active LOW.

MDIO

MDIO (input/ output): Management data I/O. This serial input/output pin is used to read from and write to the MII register.

The data value on the MDIO pin is valid and latched on the rising edge of the MDC. This pin requires a 1 k

Ω resistor pull-up.

MDC

MDC (input): Management data clock. This pin must be pulled low externally for normal operation. The MDC clock input

must be provided to allow MII management function. This pin has a Schmitt trigger input.

PHYAD1/

RXD3

PHYAD1: Resets read input. Pull high or low to set the PHY Address bit 1 for MII management function.

RXD3: Receives the data output signal in the MII interface.

PHYAD2/

RXD2

PHYAD2: Resets read input. Pull high or low to set the PHY Address bit 2 for MII management function.

RXD2: Receives the data output signal in the MII interface.

PHYAD3/

RXD1

PHYAD3 (Reset Read Input): Pull High or Low to set the PHY Address bit 3 for MII management function.

RXD1: Receive data output signal in MII interface.

PHYAD4/

RXD0

PHYAD4: Resets read input. Pull high or low to set the PHY Address bit 4 for MII management function.

RXD0: Receives the data output signal in the MII interface.

Table 2: Pinout and Signal Definitions (Cont.)

Number

Pin Name Type Description

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