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AC101L-DS01-R 数据表(PDF) 26 Page - Broadcom Corporation. |
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AC101L-DS01-R 数据表(HTML) 26 Page - Broadcom Corporation. |
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26 / 54 page ![]() AC101L Preliminary Data Sheet 8/9/04 B roa dcom Co rpo rat ion Page 16 TP PHY Register Summary Document AC101L-DS06-R REGISTER 2: PHY IDENTIFIER 1 REGISTER REGISTER 3: PHY IDENTIFIER 2 REGISTER REGISTER 4: AUTO-NEGOTIATION ADVERTISEMENT REGISTER Table 7: Register 2: PHY Identifier 1 Register Bit Name Description Mode Default 2.[15:0] OUIa a. Based on an OUI of 0010A9 (hexadecimal) Composed of bits 3 —18 of the Organizationally Unique Identifier (OUI), respectively. RO 0022(H) Table 8: Register 3: PHY Identifier 2 Register Bit Name Description Mode Default 3.[15:10] OUIa a. Based on an OUI of 0010A9 (hexadecimal) Assigned to bits 19 — 24 of the OUI. RO 010101 3.[9:4] Model Number 6-bit manufacturer’s model number. RO 010010 3.[3:0] Revision Number 4-bit manufacturer’s revision number. RO 0001 Table 9: Register 4: Auto-Negotiation Advertisement Register Bit Name Description Mode Default 4.15 Next Page 1 = Next Page enabled. 0 = Next Page disabled. RW 0 4.14 Acknowledge This bit is set internally after receiving 3 consecutive and consistent FLP bursts. RO 0 4.[13:11] Reserved – 4.10 FDFC Full-duplex flow control. 1 = Advertise that the DTE (MAC) has implemented both the optional MAC control sublayer and the pause function as specified in Clause 31 and Annex 31B of IEEE 802.3u. 0 = MAC does not support flow control. 4.9 100BASE-T4 Technology not supported. This bit is always 0. RO 0 4.8 100BASE-TX Full-Duplex 1 = 100BASE-TX full-duplex capable. 0 = Not 100BASE-TX full-duplex capable. Default value: SPD100 && DUPLEX. RW See description 4.7 100BASE-TX 1 = 100BASE-TX half-duplex capable. 0 = Not TX half-duplex capable. Default value: SPD100 && (ANEN || !DUPLEX). RW See description 4.6 10BASE-T Full Duplex 1 = 10BASE-T full-duplex capable. 0 = Not 10BASE-T full-duplex capable. Default value: DUPLEX && (ANEN || !SPD100). RW See description |
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