Preliminary Data Sheet

AC101L

8/9/04

B roa dcom Co rpo rat ion

Document

AC101L-DS06-R

Pin Descriptions

Page 7

Section 2: Pin Des c r i ptions

Many pins perform multiple functions. These pins are designated by a bold pin number, and their descriptions are listed in

the proper sections. Designers must verify that they have taken into account all modes of operation prior to final design.

Signal types:

•

B

= Bidirection pin

•

P= Power pin

•

G = Ground pin

•

AI = Analog Input pin

•

AO = Analog output pin

•

D = Internal pull-down pin

•

U = Internal pull-up pin

•

Overline = Active low

All digital pins are bidirectional pins.

Table 2: Pinout and Signal Definitions

Pin

Number

Pin Name Type Description

1

VCC

P

+2.5V power supply.

2

GND

G

Ground.

2

GND

G

Ground.

3RXDV

RXDV (active HIGH output): Receive Data Valid is the output signal in the MII mode. RXDV is active HIGH to indicate that

the receive frame is in progress, and that the data stream present on the RXD output pins is valid.

4RX_CLK

Input function is reserved. This pin must be pulled low externally.

RX_CLK (Output): Receive clock in MII mode. RX_CLK is 25-MHz output in 100BASE and 2.5 MHz output in 10BASE. This

clock is recovered from the incoming data on the cable inputs.

5RXER

Input function is reserved. This pin must be pulled low externally.

RXER (active HIGH output): asserted to indicate that an invalid symbol or bad SSD is detected in MII modes.

6

GND

G

Ground.

7

VCC

P

+2.5V power supply.

8

TXER

TXER (active HIGH input): Transmits an error in the MII interface. When TXER is asserted for one or more TX_CLK periods

while TXEN is also asserted, the PHY emits one or more symbols that are not part of the valid data or delimiter set

somewhere in the frame being transmitted. The relative position of the error within the frame need not be preserved.

9TX_CLK

TX_CLK (output): Transmits the clock signal of the MII mode. TX_CLK is

25-MHz output in 100BASE operation and 2.5-MHz in 10BASE operation. This clock is a continuously-driven output,

generated from the XI (crystal input) pin.

10

TXEN

TXEN (active HIGH input): Transmits the Enable signal in the MII interfaces. TXEN is asserted by the MAC to indicate that

valid data are present on TXD[3:0].

11

TXD0

TXD0: Transmits data input for the MII interface.

12

TXD1

TXD1: Transmits data input for the MII interface.

13

TXD2

TXD2: Transmits data input for the MII interface.

14

TXD3

TXD3: Transmits data input for MII interface.

15

COL

COL (active HIGH output): This pin must be pulled low externally. It is the collision detect signal in the MII interface. In half-

duplex mode, COL active HIGH output indicates that a collision has occurred. In full-duplex mode, COL remains low.

16

REPEATER/

CRS

REPEATER: Resets read input. Active HIGH puts the chip in repeater mode.

CRS (active HIGH output): Carrier sense signal in the MII interface. CRS is asserted when the twisted-pair media is non-

idle and is deasserted when idle, or when a valid end-of-stream delimiter is detected.

17

GND

G

Ground.

18

VCC

P

+2.5V power supply.

19

PHYAD0/

INTR

PHYAD0: Resets read input. Pull high or low to set the PHY Address bit 0 for the MII management function.

INTR (output): Active low Interrupt output. Cleared by reading register 17.