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AC101L-DS01-R 数据表(PDF) 29 Page - Broadcom Corporation.

部件名 AC101L-DS01-R
功能描述  Ultra Low-Power 10/100 Ethernet Transceiver with Auto-MDIX
PDF  54 Pages
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制造商  BOARDCOM [Broadcom Corporation.]
网页  http://www.broadcom.com
标志 BOARDCOM - Broadcom Corporation.

AC101L-DS01-R 数据表(HTML) 29 Page - Broadcom Corporation.

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Preliminary Data Sheet
AC101L
8/9/04
B roa dcom Co rpo rat ion
Document
AC101L-DS06-R
TP PHY Register Summary
Page 19
REGISTER 17: INTERRUPT CONTROL/STATUS REGISTER
REGISTER 18: DIAGNOSTIC REGISTER
16.5
Autopolarity
Disable
1 = Disables autopolarity detection/correction.
0 = Enables autopolarity detection/correction.
RW
0
16.4
Reverse
Polarity
1 = Reverses polarity when register 16.5 = 0.
0 = Normal polarity when register 16.5 = 0.
If register 16.5 is set to 1, writing a 1 to this bit reverses the
polarity of the transmitter.
RW
0
16.[3:0]
Reserved
–
RO
0
Table 14: Register 17: Interrupt Control/Status Register
Bit
Name
Description
Mode
Default
17.15
Jabber_IE
Jabber interrupt enable.
RW
0
17.14
RXER_IE
Receive error interrupt enable.
RW
0
17.13
Page_Rx_IE
Page received interrupt enable.
RW
0
17.12
PD_Fault_IE
Parallel detection fault interrupt enable.
RW
0
17.11
LP_Ack_IE
Link partner acknowledge interrupt enable.
RW
0
17.10
Link_Status_Change_I
E
Link status change interrupt enable.
RW
0
17.9
R_Fault_IE
Remote fault interrupt enable.
RW
0
17.8
ANEN_Comp_IE
Auto-negotiation complete interrupt enable.
RW
0
17.7
Jabber_Int
This bit is set when a jabber event is detected.
RC
0
17.6
RXER_Int
This bit is set when RXER transitions HIGH.
RC
0
17.5
Page_Rx_Int
This bit is set when a new page is received during ANEN.
RC
0
17.4
PD_Fault_Int
This bit is set when parallel detect fault is detected.
RC
0
17.3
LP_Ack_Int
This bit is set when the FLP with acknowledge bit set is
received.
RC
0
17.2
Link_Not_OK Int
This bit is set when link status switches from OK status to
Non-OK status (fail or ready).
RC
0
17.1
R_Fault_Int
This bit is set when remote fault is detected.
RC
0
17.0
ANEN _Comp Int
This bit is set when ANEN is complete.
RC
0
Table 15: Register 18: Diagnostic Register
Bit
Name
Description
Mode
Default
18.[15]
Reserved
Reserved.
RW
0
18.[14]
Reserved
Reserved.
RW
0
18.[13]
Force Link Pass 10BT
1 = Enables force link pass 10BASE-T.
0 = Disables force link pass 10BASE-T.
RW
0
18.[12]
Force Link Pass
100TX
1 = Force link pass 100BASE-TX.
0 = Disable Force link pass 100BASE-TX.
RW
0
18.11
Reserved
Reserved.
RO
0
Table 13: Register 16: BT and Interrupt Level Control Register (Cont.)
Bit
Name
Description
Mode
Default



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