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AC101L-DS00-R 数据表(PDF) 41 Page - Broadcom Corporation. |
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AC101L-DS00-R 数据表(HTML) 41 Page - Broadcom Corporation. |
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41 / 54 page ![]() Preliminary Data Sheet AC101L 8/9/04 B roa dcom Co rpo rat ion Document AC101L-DS06-R 100BASE-TX/FX MII Transmit System Timing Page 31 100BASE-TX/FX MII RECEIVE SYSTEM TIMING Table 39: 100BASE-TX/FX MII Receive System Timing Parameter Symbol Conditions Min Typ Max Units RX_CLK period tCK – 39.998 40.000 40.002 ns RX_CLK high period tCKH – 18.000 20.000 22.000 ns RX_CLK low period tCKL – 18.000 20.000 22.000 ns /J/K to RXDV assert tRDVA – – 40 180 ns /J/K to CRS assert tRCSA – – 40 180 ns /J/K to COL assert tRCLA RPTR is logic low. – 40 180 ns /T/R to !RXDV tRDVD RPTR is logic low. – 40 180 ns /T/R to !CRS tRCSD RPTR is logic low. – 40 180 ns /T/R to !COL tRCLD RPTR is logic low. – 40 180 ns RX propagation delay tRDVA From RXIP/N(FXRP/N) to RXD[3:0]. – 40 180 ns RXD[3:0], RXDV assert: Output delay tpLH100 From rising edge RX_CLK. 10 – 30 ns RXD[3:0], RXDV de-assert: invalid tpHL100 From rising edge RX_CLK. 10 – 30 ns |
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