5220-DS01-R datasheet(49/90 Pages) BOARDCOM

49 / 90 page

Preliminary Data Sheet

BCM5220

04/20/04

Broa d c om Co rp o r a t i o n

Document

5220-DS04-405-R

Auto-Negotiation Link Partner (LP) Next Page Transmit Register

Page 37

100BASE-X AUXILIARY CONTROL REGISTER

Transmit Disable

The transmitter can be disabled by writing a 1 to bit 13 of MII register 10h. The transmitter output (TD±) is forced into a high

impedance state.

Bypass 4B5B Encoder/Decoder

The 4B5B encoder and decoder can be bypassed by writing a 1 to bit 10 of MII register 10h. The transmitter sends 5B codes

from the TXER and TXD3, TXD2, TXD1,TXD0 pins directly to the scrambler. TXEN must be active and frame encapsulation

(insertion of J/K and T/R codes) is not performed. The receiver places descrambled and aligned 5B codes onto the RXER,

RXD3, RXD2, RXD1 and RXD0 pins. CRS can be asserted when a valid frame is received.

Bypass Scrambler/Descrambler

The stream cipher function can be disabled by writing a 1 to bit 9 of MII register 10h. The stream cipher function is re-enabled

by writing a 0 to this bit.

Table 17: 100BASE-X Auxiliary Control Register (Address 16d, 10h)

Bit

Name

R/W

Description

Default

15:14

Reserveda

a. Preserve existing values of reserved bits by completing a “Read/Modify Write.”

Write as 0, Ignore when read

Transmit Disable

R/W

1 = Transmitter disabled in PHY

0 = Normal operation

Reserveda

R/W

Write as 0, Ignore when read

Reserveda

Write as 0, Ignore when read

Reserveda

R/W

Write as 0, ignore when read

Bypass Scrambler/

Descrambler

R/W

1 = Scrambler and descrambler disabled

0 = Scrambler and descrambler enabled

Bypass NRZI Encoder/

Decoder

R/W

1 = NRZI encoder and decoder is disabled

0 = NRZI encoder and decoder is enabled

Bypass Receive Symbol

Alignment

R/W

1 = 5B receive symbols not aligned

0 = Receive symbols aligned to 5B boundaries

Baseline Wander Correction

Disable

R/W

1 = Baseline wander correction disabled

0 = Baseline wander correction enabled

FEF Enable

R/W

1 = Far end fault enabled

0 = Far end fault disabled

4:3

Reserveda

R/W

Write as 0, Ignore when read

Extended FIFO Enable

R/W

1 = Extended FIFO mode, 0 = Normal FIFO mode

Reserveda

R/W

Write as 0, ignore when read

Reserveda

R/W

Write as 0, Ignore when read

Notes: R/W = Read/Write, RO = Read only, SC = Self Clear, LL = Latched Low, LH = Latched High, LL & LH Clear after

read operation. Use default values of reserved bit(s) when writing to reserved bit(s).

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