5220-DS01-R datasheet(70/90 Pages) BOARDCOM

70 / 90 page

BCM5220

Preliminary Data Sheet

04/20/04

Broa d c om Co rp o r a t i o n

Page 58

Auxiliary Status 4 Register (Shadow Register)

Document

5220-DS04-405-R

Se ction 6: Timing an d AC Char acte r istics

The timing information contained in this section applies to the BCM5220.

All MII Interface pins comply with IEEE 802.3u timing specifications (see Reconciliation Sublayer and Media Independent

Interface in IEEE 802.3u timing specifications). All digital output timing specified at CL = 30 pF.

Output rise/fall times measured between 10% and 90% of the output signal swing. Input rise/fall times measured between

VIL max. and VIH min. Output signal transitions referenced to the midpoint of the output signal swing. Input signal transitions

referenced to the midpoint between VIL max. and VIH min. See Table 37 and Table 38 for the timing parameters. See

Figure 3 for an illustration of clock and reset timing.

Table 37: Clock Timing

Parameter

Symbol

Min

Typ

Max

Unit

XTALI Cycle Time

CK_CYCLE

39.998

40.002

XTALI High/Low Time

CK_HI

CK_LO

REF_CLK Cycle Time (MII - 25 MHz)

REF_CLK High/Low Time (MII - 25 MHz)

REF_CLK Rise/Fall Time (MII - 25 MHz)

REF_CLK Cycle Time (RMII - 50 MHz)

REF_CLK High/Low Time (RMII - 50 MHz)

REF_CLK Rise/Fall Time (RMII - 50 MHz)

Table 38: Reset Timing

Parameter

Symbol

Min

Typ

Max

Unit

Reset Pulse Length with stable XTALI Input (see

note)

RESET_LEN

400

Activity after end of Hardware Reset

RESET_WAIT

100

µs

RESET# Rise/Fall Time

RESET_EDGE

Note: During power-on, RESET# pin must be held low to get the BCM5220 to power-up in normal mode.

5220-DS01-R 数据表(PDF) 70 Page - Broadcom Corporation.

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