BT8376EPF datasheet(86/323 Pages) CONEXANT

部件名	BT8376EPF

功能描述	single chip transceivers for T1/E1 and Integrated Service Digital Network (ISDN) primary rate interfaces

PDF	323 Pages

Scroll/Zoom	100%

制造商	CONEXANT [Synaptics Incorporated.]

网页	https://www.synaptics.com/

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86 / 323 page

2.0 Circuit Description

Bt8370/8375/8376

2.8 Transmitter

Fully Integrated T1/E1 Framer and Line Interface

2-58

Conexant

N8370DSE

Bt8370/8375/8376 uses a hierarchical interrupt structure, with 1 top-level

Interrupt Request register [IRR; addr 003] directing software to the lower levels.

Of all the interrupt sources, the 2 most significant bandwidth requirements are

signaling and data link interrupts. Each data link controller has a top-level

interrupt status register that reports data link operations (see Data Link 1 and 2

Interrupt Status registers [ISR2; addr 009, and ISR1; 00A]). The processor uses a

2-step interrupt scheme for the data link: it reads the Interrupt Request register,

then uses that register value to read the corresponding Data Link Interrupt Status

Figure 2-31. Interrupt Driven Transmit Data Link Processing

Transmit Message

Write Block/Byte to FIFO

Process Other Interrupt

Yes

Return

Write Block/Byte to FIFO

End of

Message

Yes

Message

Block 1

Block 2

Block 3

0x00

0x20

0x40

Main Line Code

Return

Interrupt Service Routine

Interrupt Occurred

Read Interrupt Status

Transmit Data

Link Near Empty

Interrupt

Return

Write End of Message Register

Return

Block 4

0x60

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