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BT8376EPF 数据表(PDF) 22 Page - Synaptics Incorporated.

部件名 BT8376EPF
功能描述  single chip transceivers for T1/E1 and Integrated Service Digital Network (ISDN) primary rate interfaces
PDF  323 Pages
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制造商  CONEXANT [Synaptics Incorporated.]
网页  https://www.synaptics.com/
标志 CONEXANT - Synaptics Incorporated.

BT8376EPF 数据表(HTML) 22 Page - Synaptics Incorporated.

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1.0 Pin Descriptions
Bt8370/8375/8376
1.1 Pin Assignments
Fully Integrated T1/E1 Framer and Line Interface
1-6
Conexant
N8370DSE
Digital Transmitter (XMTR) (Continued)
TPOSI
TX Positive Rail Input
I
Line rate data input on TCKI falling edge. Replaces all data that would
otherwise be supplied by ZCS encoder. Bt8370/8375/8376 default power
on state selects TPOSI/TNEGI as source for all transmitted XTIP/XRING
output pulses, encoded as follows:
TNEGI
TX Negative Rail Input
I
Line rate data input on TCKI falling edge. Replaces all data that would
otherwise be supplied by ZCS encoder. Refer to TPOSI signal definition.
TPOSO
TX Positive Rail
Output
O
Line rate data output from ZCS encoder or JAT on rising edge of TCKO.
Active-high marks transmission of a positive AMI pulse. Used to monitor
transmit data or for systems that employ an external line interface unit.
TNEGO
TX Negative Rail
Output
O
Line-rate data output from ZCS encoder or JAT on rising edge of TCKO.
Active-high marks transmission of a negative AMI pulse. Used to monitor
transmit data or for systems that use an external line interface unit.
TDLI
TX Data Link Input
I
Selected time slot bits are sampled on TDLCKO falling edge for insertion
into the transmit output stream during external data link applications.
TDLCKO
TX Data Link Clock
O
Gapped version of TCKI for external data link applications. TDLCKO high
clock pulse coincides with low TCKI pulse interval during selected time
slot bits (see [DL3_TS; addr 015]).
TCKO
TX Clock Output
O
Line rate clock used to align XTIP/XRING outputs. If transmit jitter
attenuator (TJAT) is disabled, TCKO equals selected TCKI or ACKI. If TJAT
is enabled, TCKO equals the jitter attenuated clock (JCLK).
TNRZO
TX Non Return to
Zero Data
O
Line rate data output from transmitter on rising edge of TCKI. TNRZO does
not include ZCS encoded bipolar violations.
MSYNCO
TX Multiframe Sync
O
Active-high for 1 TCKI clock cycle to mark the first bit of TX multiframe
coincident with TNRZO. Output on rising edge of TCKI.
Table 1-1. Hardware Signal Definitions (3 of 8)
Pin Label
Signal Name
I/O
Definition
TPOSI
TNEGI
TX Pulse Polarity
0
0
No pulse
0
1
Negative AMI pulse
1
0
Positive AMI pulse
11
Invalid
NOTE(S):
Software must set TDL_IO (addr 018) to enable normal
data from internal transmitter.



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