ADE7760

Rev. 0 | Page 12 of 24

*RB + VR = RF

VR*

RB*

RA*

±660mV

AGND

Figure 12. Typical Connection for Channel 2

INTERNAL OSCILLATOR

The nominal internal oscillator frequency is 450 kHz when

between RCLKIN and DGND (see Figure 13).

The internal oscillator frequency is inversely proportional to the

value of this resistor. Although the internal oscillator operates

is recommended to choose a value within the range of the

nominal value.

The output frequencies on CF, F1, and F2 are directly

proportional to the internal oscillator frequency; thus, the

drift. A low tolerance resistor limits the variation of the internal

oscillator frequency. Small variation of the clock frequency and

consequently of the output frequencies from meter to meter

contributes to a smaller calibration range of the meter. A low

temperature drift resistor directly limits the variation of the

internal clock frequency over temperature. The stability of the

meter to external variation is then better ensured by design.

2.5V

REFERENCE

INTERNAL

OSCILLATOR

9

ADE7760

DGND

RCLKIN

4k

Ω

14

17

Figure 13. ADE7760 Internal Oscillator Connection

ANALOG-TO-DIGITAL CONVERSION

The analog-to-digital conversion in the ADE7760 is carried out

using second-order Σ-Δ ADCs. Figure 14 shows a first-order

(for simplicity) Σ-Δ ADC. The converter is made up of two

parts, the Σ-Δ modulator and the digital low-pass filter.

....10100101....

1-BIT DAC

LATCHED

COMPAR-

ATOR

INTEGRATOR

MCLK

∫

C

R

ANALOG

LOW-PASS FILTER

DIGITAL

LOW-PASS FILTER

1

24

Figure 14. First-Order Σ-∆ ADC

A Σ-Δ modulator converts the input signal into a continuous

serial stream of 1s and 0s at a rate determined by the sampling

clock. In the ADE7760, the sampling clock is equal to CLKIN.

The 1-bit DAC in the feedback loop is driven by the serial data

stream. The DAC output is subtracted from the input signal. If

the loop gain is high enough, the average value of the DAC

output (and, therefore, the bit stream) approaches that of the

input signal level. For any given input value in a single sampling

interval, the data from the 1-bit ADC is virtually meaningless.

Only when a large number of samples are averaged is a

meaningful result obtained. This averaging is carried out in the

second part of the ADC, the digital low-pass filter. By averaging

a large number of bits from the modulator, the low-pass filter

can produce 24-bit data words that are proportional to the input

signal level.

The Σ-Δ converter uses two techniques to achieve high resolu-

tion from what is essentially a 1-bit conversion technique. The

first is oversampling, which means that the signal is sampled at

a rate (frequency) that is many times higher than the bandwidth

of interest. For example, the sampling rate in the ADE7760 is

CLKIN (450 kHz) and the band of interest is 40 Hz to 1 kHz.

Oversampling has the effect of spreading the quantization noise

(noise due to sampling) over a wider bandwidth. With the noise

spread more thinly over a wider bandwidth, the quantization

noise in the band of interest is lowered (see Figure 15).

However, oversampling alone is not an efficient enough method

to improve the signal-to-noise ratio (SNR) in the band of inter-

est. For example, an oversampling ratio of 4 is required just to

increase the SNR by only 6 dB (1 bit). To keep the oversampling

ratio at a reasonable level, it is possible to shape the quantization

noise so that the majority of the noise lies at the higher frequen-

cies. This is what happens in the Σ-Δ modulator; the noise is

shaped by the integrator, which has a high-pass type response

for the quantization noise. The result is that most of the noise is

at the higher frequencies where it can be removed by the digital

low-pass filter. This noise shaping is also shown in Figure 15.