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ADE7760ARS 数据表(PDF) 16 Page - Analog Devices

部件名 ADE7760ARS
功能描述  Energy Metering IC with On-Chip Fault Detection
PDF  24 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADE7760ARS 数据表(HTML) 16 Page - Analog Devices

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ADE7760
Rev. 0 | Page 16 of 24
The output frequency on CF can be up to 2048 times higher
than the frequency on F1 and F2. This higher output frequency
is generated by accumulating the instantaneous active power
signal over a much shorter time while converting it to a
frequency. This shorter accumulation period means less
averaging of the cos(2ωt) component. As a consequence, some
of this instantaneous power signal passes through the digital-to-
frequency conversion. This is not a problem in the application.
Where CF is used for calibration purposes, the frequency
should be averaged by the frequency counter, which removes
any ripple. If CF is being used to measure energy, such as in a
microprocessor-based application, the CF output should also be
averaged to calculate power. Because the outputs F1 and F2
operate at a much lower frequency, a lot more averaging of the
instantaneous active power signal is carried out. The result is a
greatly attenuated sinusoidal content and a virtually ripple-free
frequency output.
TRANSFER FUNCTION
Frequency Outputs F1 and F2
The ADE7760 calculates the product of two voltage signals (on
Channel 1 and Channel 2) and then low-pass filters this product
to extract active power information. This active power
information is then converted to a frequency. The frequency
information is output on F1 and F2 in the form of active high
pulses. The pulse rate at these outputs is relatively low, for
example, 0.34 Hz maximum for ac signals with S0 = S1 = 0
(see Table 7). This means that the frequency at these outputs is
generated from active power information accumulated over a
relatively long period of time. The result is an output frequency
that is proportional to the average active power. The averaging
of the active power signal is implicit to the digital-to-frequency
conversion. The output frequency or pulse rate is related to the
input voltage signals by the following equation:
2
2
70
.
5
REF
4
1
rms
rms
1
V
F
V2
V1
Frequency
F
F
×
×
×
=
(7)
where:
F1 − F2 Frequency is the output frequency on F1 and F2 (Hz).
V1rms is the differential rms voltage signal on Channel 1 (V).
V2rms is the differential rms voltage signal on Channel 2 (V).
VREF is the reference voltage (2.5 V ± 8%) (V).
F1–4 is one of four possible frequencies selected by using the
logic inputs S0 and S1 (see Table 5).
Table 5. F1–4 Frequency Solution
S1
S0
F1–4 (Hz)1
OSC/CLKIN2
0
0
1.72
OSC/218
0
1
3.44
OSC/217
1
0
6.86
OSC/216
1
1
13.7
OSC/215
1 Values are generated using the nominal frequency of 450 kHz.
2 F1–4 are a binary fraction of the master clock and, therefore, varies, if the
internal oscillator frequency (OSC).
Frequency Output CF
The pulse output calibration frequency (CF) is intended for use
during calibration. The output pulse rate on CF can be up to
2048 times the pulse rate on F1 and F2. The lower the F1–4
frequency selected, the higher the CF scaling. Table 6 shows
how the two frequencies are related, depending on the states of
the logic inputs S0, S1, and SCF. Because of its relatively high
pulse rate, the frequency at this logic output is proportional to
the instantaneous active power. As with F1 and F2, the fre-
quency is derived from the output of the low-pass filter after
multiplication. However, because the output frequency is high,
this active power information is accumulated over a much
shorter time. Therefore, less averaging is carried out in the
digital-to-frequency conversion. With much less averaging of
the active power signal, the CF output is much more responsive
to power fluctuations (see Figure 17).
Table 6. Relationship between CF and F1, F2 Frequency
Outputs
SCF
S1
S0
F1–4 (Hz)
CF Frequency output
1
0
0
1.72
128 × F1, F2
0
0
0
1.72
64 × F1, F2
1
0
1
3.44
64 × F1, F2
0
0
1
3.44
32 × F1, F2
1
1
0
6.86
32 × F1, F2
0
1
0
6.86
16 × F1, F2
1
1
1
13.7
16 × F1, F2
0
1
1
13.7
2048 × F1, F2
Example
In this example, if ac voltages of ±660 mV peak are applied to
V1 and V2, then the expected output frequency on CF, F1, and
F2 is calculated as follows:
F1–4 = 1.7 Hz, SCF = S1 = S0 = 0
V1rms = rms of 660 mV peak ac = 0.66/√2 V
V2rms = rms of 660 mV peak ac = 0.66/√2 V
VREF = 2.5 V (nominal reference value)



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