ADCMP573BCP datasheet(6/16 Pages) AD

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ADCMP572/ADCMP573

Preliminary Technical Data

Rev. PrB | Page 6 of 16

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

ADCMP572

ADCMP573

TOP VIEW

(Not to Scale)

VTP

PIN1

VTN

VCCO

Figure 2. ADCMP572/ADCMP573 Pin Configuration

Table 3. Pin Function Descriptions

Pin No.

Mnemonic

Description

VTP

Termination Resistor Return Pin for VP Input.

Noninverting Analog Input.

Inverting Analog Input.

VTN

Termination Resistor Return Pin for VN Input.

5, 16

VCCI

Positive Supply Voltage for Input Stage.

Latch Enable Input Pin, Inverting Side.

In compare mode (LE = low), the output tracks changes at the input of the comparator.

In latch mode (LE = high), the output reflects the input state just prior to the comparator’s being

placed in latch mode. LE must be driven in compliment with LE.

Latch Enable Input Pin, Noninverting Side.

In compare mode (LE = high), the output tracks changes at the input of the comparator.

In latch mode (LE = low), the output reflects the input state just prior to the comparator’s being

placed in latch mode. LE must be driven in compliment with LE.

VCCO/VTT

Termination Return Pin for the LE/LE Input Pins.

For the ADCMP572 (CML output stage), this pin should be connected to the positive VCCO supply.

For the ADCMP573 (RSPECL output stage), this pin should be connected to the VCCO – 2 V

termination potential.

13, 15

GND

Ground.

9, 12

VCCO

Positive Supply Voltage for the CML/RSPECL Output Stage.

Inverting Output. Q is at logic low if the analog voltage at the noninverting input, VP, is greater than

the analog voltage at the inverting input, VN, provided the comparator is in compare mode. See the

LE/LE description (Pins 6 and 7) for more information.

Noninverting Output. Q is at logic high if the analog voltage at the noninverting input VP is greater

than the analog voltage at the inverting input, VN, provided the comparator is in compare mode. See

the LE/LE description (Pins 6 and 7) for more information.

HYS

Hysteresis Control Pin. Leave this pin disconnected for zero hysteresis. Connect to GND with a

suitably sized resistor to add the desired amount of hysteresis. Refer to Figure 7 for proper sizing of

RHYS hysteresis control resistor.

Heatsink

N/C

The metallic back surface of the package is not electrically connected to any part of the circuit, and it

can be left floating for best electrical isolation between the package handle and the substrate of the

die. But it can also be soldered to the application board if improved thermal and/or mechanical

stability is desired.

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