ADCMP572/ADCMP573

Preliminary Technical Data

Rev. PrB | Page 12 of 16

TYPICAL APPLICATION CIRCUITS

Q

3.3V

50

Ω

50

Ω

ADCMP572

Q

LATCH

INPUTS

Figure 18. Zero-Crossing Detector with 3.3 V CML Outputs

Q

50

Ω

50

Ω

Q

LATCH

INPUTS

ADCMP572

Figure 19. LVDS to50 Ω Back-Terminated (RS)PECL Receiver

50

Ω

50

Ω

+

–

Q

Q

LATCH

INPUTS

GND = –1V

2.5V/3.3V

ADCMP572

Figure 20. Comparator with ±1 V Input Range and

2.5 V or 3.3 V CML Outputs

50

Ω

50

Ω

Q

Q

LATCH

INPUTS

3.3V/5.2V

ADCMP572

Figure 21. Comparator with 0 V to 3 V Input Range and

3.3 V or 5.2 V Positive CML Outputs

LATCH

INPUTS

5V

75

Ω

50

Ω

50

Ω

100

Ω

100

Ω

ADCMP572

Figure 22. Interfacing 3.3 V CML to a 50 Ω

Ground Terminated Instrument

750

Ω

ADCMP572

50

Ω

50

Ω

Figure 23. Disabling the Latch Feature

HYS

ADCMP572

50

Ω

50

Ω

0

Ω TO 5kΩ

Figure 24. Adding Hysteresis Using the HYS Control Pin