ADCMP572/ADCMP573

Preliminary Technical Data

Rev. PrB | Page 10 of 16

external 500 Ω resistor, and leaving the LE pin disconnected. In

OPTIMIZING HIGH SPEED PERFORMANCE

As with any high speed comparator, proper design and layout

techniques are essential to obtaining the specified performance.

Stray capacitance, inductance, inductive power and ground

impedances, or other layout issues can severely limit performance

and can often cause oscillation. Discontinuities along input and

output transmission lines can also severely limit the specified

pulse-width dispersion performance.

For applications working in a 50 Ω environment, input and

output matching has a significant impact on data dependant (or

deterministic) jitter (DJ) and pulse-width dispersion perform-

ance. The ADCMP572/ADCMP573 comparators provide

and the ADCMP572 provides 50 Ω back terminated outputs.

The return side for each input termination is pinned out

(from) the desired termination potential as required. The

termination potential should be carefully bypassed using high

quality bypass capacitors as discussed above to prevent undesired

aberrations on the input signal due to parasitic inductance in

the circuit board layout. If a 50 Ω input termination is not

be left disconnected. In this case, the pins should be left floating

with no external pull-downs or bypassing capacitors.

It should be understood that when leaving an input termination

disconnected, the internal resistor acts as a small stub on the

input transmission path and can cause problems for very high

speed inputs. Reflections should then be expected from the

comparator inputs because they no longer provide a matched

impedance to the input path leading to the device. It then

becomes important to back-match the drive source impedance

to the input transmission path to minimize multiple reflections.

For applications in which the comparator is very close to the

driving signal source, the source impedance should be mini-

mized. High source impedance in combination with parasitic

input capacitance of the comparator could cause an undesirable

degradation in bandwidth at the input, thus degrading the overall

response. Although the ADCMP572/ ADCMP573 comparators

have been designed to minimize input capacitance, some parasitic

capacitance is inevitable. It is therefore recommended that the

drive source impedance be no more than 50 Ω for best high

speed performance.

COMPARATOR PROPAGATION

DELAY DISPERSION

The ADCMP572/ADCMP573 comparators are designed to

reduce propagation delay dispersion over a wide input overdrive

range of 5 mV to 500 mV. Propagation delay dispersion is a

variation in propagation delay that results from a change in the

degree of overdrive or slew rate (how far or how fast the input

signal exceeds the switching threshold).

Propagation delay dispersion is a specification that becomes

important in high speed time critical applications such as data

communication, automatic test and measurement, instrumenta-

tion, and event-driven applications such as pulse spectroscopy,

nuclear instrumentation, and medical imaging. Dispersion is

defined as the variation in propagation delay as the input over-

drive conditions are changed (Figure 14 and Figure 15). For the

ADCMP572/ADCMP573, dispersion is typically <15 ps because

the overdrive is varied from 10 mV to 500 mV, and the input

slew rate is varied from 2 V/ns to 10 V/ns. This specification

applies for both positive and negative signals since the

ADCMP572/ADCMP573 has substantially equal delays for

either positive-going or negative-going inputs.

Q/Q OUTPUT

INPUT VOLTAGE

500mV OVERDRIVE

10mV OVERDRIVE

DISPERSION

Figure 14. Propagation Delay—Overdrive Dispersion

Q/Q OUTPUT

INPUT VOLTAGE

10V/ns

1V/ns

DISPERSION

Figure 15. Propagation Delay—Slew Rate Dispersion