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HCS370IP 数据表(PDF) 12 Page - Microchip Technology |
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HCS370IP 数据表(HTML) 12 Page - Microchip Technology |
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12 / 36 page ![]() HCS370 DS41111D-page 12 Preliminary 2002 Microchip Technology Inc. FIGURE 3-2: CODE WORD DATA FORMAT (20-BIT COUNTER) 3.2.3.1 Low Voltage Detector Status (VLOW) A low battery voltage detector onboard the HCS370 can indicate when the operating voltage drops below a predetermined value. There are two options available depending on the Low Voltage Trip Point Select (VLOWSEL) configuration option. The two options pro- vided are: • A 2.2V nominal level for 3V operation • A 3.2V nominal level for 5V operation The output of the low voltage detector is checked on the first preamble pulse of each code word with the LED momentarily turned off. The VLOW bit is transmit- ted in each code word so the decoder can give an indi- cation to the user that the transmitter battery is low. Operation of the LED changes as well to further indi- cate that the battery is low and needs replacing. The output of the Low Voltage Detector can also be latched once it has dropped below the selected value. The Low Voltage Latch (VLOWL) configuration option enables this option. If this option is enabled, the detec- tor level is raised to 3V or 5V once a low battery voltage has been detected, like a Schmitt Trigger. This will effectively hold the VLOW bit high until the bat- tery is replaced. If the Low Voltage Latch is enabled, then the low TE after the first preamble pulse can stretch by 4 ms one time as the latch changes state. Transmission Direction LSB First Fixed Code Portion (32 Bits) QUE 2 Bits CRC 2 Bits VLOW 1-Bit SERIAL NUMBER (28 Bits) Q1 Q0 C1 C0 S2 S1 S0 S3 BUT 4 Bits DISC 8 Bits Synchronization 20 Bits Counter 19 0 S2 S1 S0 S3 Hopping Code Portion (32 Bits) With XSER=0, 20-bit Counter, QUEN=1 Status Information (5 Bits) BUT 4 Bits Fixed Code Portion (32 Bits) CRC 2 Bits VLOW 1-Bit SERIAL NUMBER (32 Bits) C1 C0 BUT 4 Bits DISC 8 Bits Synchronization 20 Bits Counter 19 0 S2 S1 S0 S3 Hopping Code Portion (32 Bits) With XSER=1, 20-bit Counter, QUEN=0 Status Information (3 Bits) |
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