| 数据搜索系统,热门电子元器件搜索 |
|
MP8763GL 数据表(PDF) 17 Page - Monolithic Power Systems |
|
|
|||||||||||||||||||||||||||||
MP8763GL 数据表(HTML) 17 Page - Monolithic Power Systems |
|
17 / 24 page ![]() MP8763 — 12A, 18V, SYNCHRONOUS STEP-DOWN CONVERTER MP8763 Rev. 1.3 www.MonolithicPower.com 17 6/21/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. APPLICATION INFORMATION Output-Voltage, Large-ESR Capacitors For applications that use electrolytic or POS capacitors with large ESR values as output capacitors, the feedback resistors—R1 and R2 as shown in Figure 10—set the output voltage. R1 R2 ESR POSCAP SW VOUT L FB Figure 10: Simplified POSCAP Circuit First, choose an R2 that balances between high quiescent current loss (lower R2) and high noise sensitive on FB (higher R2). A typical value falls within 5k -50k , using a comparatively larger R2 when VOUT is low, and a smaller R2 when VOUT is high. Then calculate R1 as follows: OUT OUT REF REF 1 V V V 2 R1 R2 V − × ∆ − = × (15) Where OUT V ∆ is the output ripple determined by equation 24. Output-Voltage, Small-ESR Capacitors R1 R2 Ceramic SW FB VOUT L R9 R4 C4 Figure 11: Simplified Ceramic Capacitor Circuit When using a low-ESR, ceramic capacitor on the output, add an external voltage ramp to the FB pin (R4 and C4). The ramp voltage (VRAMP) and the resistor divider (shown in Figure 11) influence the output voltage . Calculate VRAMP as shown in equation 7. Select R2 to balance between high quiescent current loss and FB noise sensitivity. Choose R2 within 5k -50k , using a larger R2 when VOUT is low, and a smaller R2 when VOUT is high. Determine the value of R1 as follows: 9 R 4 R 2 R V V V 2 R 1 R ) AVG ( FB OUT ) AVG ( FB + − − = (16) Where VFB(AVG) is the average FB voltage. VFB(AVG) varies with the VIN, VOUT, and load condition, where the load regulation is strictly related to the VFB(AVG). Also the line regulation is related to the VFB(AVG)—improving load or line regulation involves a lower VRAMP that meets equation 9. For PWM operation, estimate VFB(AVG) from equation 17. RAMP REF AVG FB V V V × + = 2 1 ) ( (17) Usually, R9 is 0 , though it can also be set following equation 18 for better noise immunity. It should also be less than 20% of R1//R2 to minimize its influence on VRAMP. 1 R1 R2 R9 5 R1 R2 × < × + (18) Using equations 16 and 17 to calculate the output voltage can be complicated. To simplify the R1 calculation in equation 16, add a DC- blocking capacitor (CDC) to filter the DC influence from R4 and R9. Figure 12 shows a simplified circuit with external ramp compensation and a DC-blocking capacitor. The addition of this capacitor simplifies the R1 calculation as per equation 19 for PWM mode operation. 2 R V 2 1 V V 2 1 V V 1 R RAMP REF RAMP REF OUT × × + × − − = (19) For best results, select a CDC value at least 10×C4 for better DC blocking performance, but smaller than 0.47uF to account for start-up performance. To use a larger CDC for better FB noise immunity, reduce R1 and R2 to limit their effects on system start-up. Note that even with CDC, the load and line regulation are still related to VRAMP. |
|
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |