MP8763 — 12A, 18V, SYNCHRONOUS STEP-DOWN CONVERTER

MP8763 Rev. 1.3

www.MonolithicPower.com

20

6/21/2016

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LAYOUT RECOMMENDATIONS

1. MPS offers two packages, but recommends

MP8763GLE with its 16-pin QFN package for

all new designs due to its smaller parasitical

inductance.

2. Place high current paths (GND, IN, and SW)

very close to the device with short, direct and

wide traces.

3. The 13-pin QFN package requires two copper

IN

layers

for

better

performance.

Respectively put at least one decoupling

capacitor on both Top and Bottom layers and

as close to the IN and GND pins as possible.

Add several vias with 18mil and 8mil hole

diameters under the device and near the

input capacitors to help dissipate heat and to

reduce parasitic inductances.

4. Place a decoupling capacitor as close to the

VCC and AGND pins as possible.

5. Keep the switching node (SW) plane as small

as possible and far away from the feedback

network.

6. Place the external feedback resistors next to

the FB pin. Make sure that there are no vias

on the FB trace. The feedback resistors

should refer to AGND instead of PGND.

7. Keep the BST voltage path (BST, C3, and

SW) as short as possible.

8. MPS strongly recommends a four-layer layout

to improve thermal performance.

Figure 13: Schematic Reference for PCB Layout

IN

R3

R1

R3

R2

R3

R4

R3

C4

R3

C2

VIN

GND

SW

VOUT

PGND

PGND

SW

SW

R3

C5

R3

R3

GND

Top Layer

GND

Inner1 Layer

GND

Inner2 Layer