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MP8763GL 数据表(PDF) 14 Page - Monolithic Power Systems

部件名 MP8763GL
功能描述  High Efficiency, 12A, 18V, Synchronous, Step-Down Converter
PDF  24 Pages
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制造商  MPS [Monolithic Power Systems]
网页  http://www.monolithicpower.com
标志 MPS - Monolithic Power Systems

MP8763GL 数据表(HTML) 14 Page - Monolithic Power Systems

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MP8763 — 12A, 18V, SYNCHRONOUS STEP-DOWN CONVERTER
MP8763 Rev. 1.3
www.MonolithicPower.com
14
6/21/2016
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2016 MPS. All Rights Reserved.
Ramp with a Small ESR Capacitor
Use an external ramp when using ceramic output
capacitors, because the ESR ripple is not high
enough to stabilize the system.
R1
R2
Ceramic
SW
FB
VOUT
L
R4
C4
IR4
IC4
IFB
R9
Figure 7: Simplified PWM-Mode Circuit with
External Ramp Compensation
Figure 7 shows the simplified circuit in PWM
mode with the HS-FET OFF and an external
ramp compensation circuit (R4, C4). Design the
external ramp based on the inductor ripple
current. Select C4, R9, R1 and R2 to meet the
following condition:
+
+
×
×
<
×
×
π
9
2
1
2
1
5
1
4
2
1
R
R
R
R
R
C
f
SW
(5)
Where:
4
C
FB
4
C
4
R
I
I
I
I
+
=
(6)
Then estimate the ramp on VFB as:
+
×
τ
×
×
=
9
2
1
2
1
4
4
R
R
//
R
R
//
R
C
R
V
V
V
ON
OUT
IN
RAMP
(7)
The VFB ripple’s descending slope is then:
4
4
1
C
R
V
V
V
OUT
OFF
RAMP
SLOPE
×
=
τ
=
(8)
Equation 8 shows that if there is instability in
PWM mode, reduce either R4 or C4. If C4 is
irreducible due to limitations from equation 5,
then reduce R4. For stable PWM operation,
design Vslope1 based on equation 9.
SW
ON
3
ESR
OUT
OUT
SLOPE1
OUT
OUT
SW
ON
T
T
R
C
I
10
0.7
2
V
V
2 L C
T
T
+
×
×
× π
×
+
× ×
(9)
Where IOUT is the load current.
In skip mode, the VFB ripple’s descending slope is
almost the same whether the external ramp is
used or not. Figure 8 shows the simplified circuit
in skip mode when both the HS-FET and LS-FET
are off.
R1
R2
COUT
FB
VOUT
ROUT
Figure 8: Simplified Skip-Mode Circuit
Determine the VFB ripple’s descending slope in
skip mode as follows:
OUT
OUT
REF
2
SLOPE
C
]
R
//
)
2
R
1
R
[(
V
V
×
+
=
(10)
Where ROUT is the equivalent load resistor.
Figures 5 shows that VSLOPE2 in skip mode is
lower than it is in PWM mode, so it is reasonable
that the jitter in skip mode is larger. To achieve
less
jitter
during
ultra-light-load
conditions,
reduce R1 and R2, though that will decrease the
light-load efficiency.
Configuring the EN Control
The regulator turns on when EN goes HIGH.
Conversely it turns OFF when EN goes LOW. Do
not float the pin.
For automatic start-up, pull the EN pin up to the
input voltage through a resistive voltage divider.
Choose the values of the pull-up resistor (RUP,
from the IN pin to the EN pin) and the pull-down
resistor (RDOWN, from the EN pin to GND) to
determine the automatic start-up voltage:
UP
DOWN
IN START
DOWN
(R
R
)
V
1.5
(V)
R
+
=
×
(11)
For example, for RUP=100k
and RDOWN=20k ,
the VIN-START is set at 9V.
To reduce noise, add a 10nF ceramic capacitor
from EN to GND.
An internal zener diode on the EN pin clamps the
EN
pin
voltage
to
prevent
runaway.
The
maximum pull-up current (assuming the worst
case, 6V) for the internal zener clamp should be
less than 1mA.



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