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LTC3113

3113f

APPLICATIONS INFORMATION

The capacitors listed in Table 2 provide a sampling of small

surface mount ceramic capacitors that are well suited to

LTC3113 application circuits. All listed capacitors are either

X5R or X7R dielectric in order to ensure that capacitance

loss over temperature is minimized.

Table 2. Representative Buck-Boost Surface Input Mount Bypass

and Output Capacitors

PART NUMBER

VALUE

(μF)

VOLTAGE

(V)

SIZE (mm) W

× L × H

(FOOTPRINT)

AVX (www.avx.com)

1812D476KAT2A

6.3

3.2

× 4.5 × 2.5 (1812)

18126D107KAT2A

100

6.3

3.2

× 4.5 × 2.8 (1812)

Murata (www.murata.com)

GRM43ER60J476ME01

6.3

3.2

× 4.5 × 2.5 (1812)

GRM43SR60J107ME20

100

6.3

3.2

× 4.5 × 2.8 (1812)

GRM55FR60J107KA01L

100

6.3

× 5.7 × 3.2 (2220)

Taiyo Yuden (www.t-yuden.com)

JMK432BJ476MM-T

6.3

3.2

× 4.5 × 2.5 (1812)

JMK432C107MM-T

100

6.3

3.2

× 4.5 × 2.8 (1812)

TDK (www.component.tdk.com)

C4532X5R0J476M

6.3

3.2

× 4.5 × 2.5 (1812)

C4532X5R0J107M

100

6.3

3.2

× 4.5 × 2.5 (1812)

C5750X5R1C476M

× 5.7 × 2.5 (2220)

C5750X5R1A686M

× 5.7 × 2.5 (2220)

C5750X5R0J107M

100

6.3

× 5.7 × 2.5 (2220)

PCB LAYOUT CONSIDERATIONS

The LTC3113 switches large currents at high frequencies.

Special attention should be paid to the PCB layout to ensure

a stable, noise-free and efﬁcient application circuit. Figure

3 presents a representative 4-layer PCB layout to outline

some of the primary considerations. A few key guidelines

are outlined below:

1. All circulating high current paths should be kept as

short as possible. This can be accomplished by keeping

the routes to all highlighted components in Figure 3

as short and as wide as possible. Capacitor ground

connections should via down to the ground plane in

the shortest route possible. The bypass capacitors on

VIN should be placed as close to the IC as possible and

should have the shortest possible paths to ground.

2. The Exposed Pad is the power ground connection for

the LTC3113. Multiple vias should connect the backpad

directly to the ground plane. In addition maximization

of the metallization connected to the backpad will im-

prove the thermal environment and improve the power

handling capabilities of the IC. Refer to Figure 3d bot-

tom layer as an example of proper exposed pad power

ground and via layout to provide good thermal and

ground connection performance.

3. The components shown highlighted and their connec-

tions should all be placed over a complete ground plane

to minimize loop cross-sectional areas. This minimizes

EMI and reduces inductive drops.

4. Connections to all of the components shown highlighted

should be made as wide as possible to reduce the series

resistance. This will improve efﬁciency and maximize the

output current capability of the buck-boost converter.

5. To prevent large circulating currents from disrupting

the output voltage sensing, the ground for each resistor

divider should be returned to the ground plane using

a via placed close to the IC and away from the power

connections.

6. Keep the connection from the resistor dividers to the

feedback pins, FB, as short as possible and away from

the switch pin connections.

7. Crossover connections should be made on inner copper

layers if available. If it is necessary to place these on

the ground plane, make the trace on the ground plane

as short as possible to minimize the disruption to the

ground plane.

Thermal Considerations

The LTC3113 output current may need to be derated if

it is required to operate in a high ambient temperature

or delivering a large amount of continuous power. The

amount of current derating is dependent upon the input

voltage, output voltage and ambient temperature. The

temperature rise curves given in the Typical Performance

Characteristics section can be used as a guide. These curves

were generated by mounting the LTC3113 to a 4-layer

FR4 demo board shown in Figure 3. Boards of other sizes

and layer count can exhibit different thermal behavior, so

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