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AD8375ACPZ-R7 数据表(PDF) 13 Page - Analog Devices

部件名 AD8375ACPZ-R7
功能描述  Ultralow Distortion IF VGA
PDF  24 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD8375ACPZ-R7 数据表(HTML) 13 Page - Analog Devices

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Data Sheet
AD8375
Rev. B | Page 13 of 24
APPLICATIONS
BASIC CONNECTIONS
Figure 35 shows the basic connections for operating the
AD8375. A voltage between 4.5 V and 5.5 V should be applied
to the supply pins. Each supply pin should be decoupled with at
least one low inductance, surface-mount ceramic capacitor of
0.1 μF placed as close as possible to the device.
The outputs of the AD8375 are open collectors that need to be
pulled up to the positive supply with 1 μH RF chokes. The
differential outputs are biased to the positive supply and require
ac coupling capacitors, preferably 0.1 μF. Similarly, the input
pins are at bias voltages of about 2 V above ground and should
be ac-coupled as well. The ac coupling capacitors and the RF
chokes are the principle limitations for operation at low
frequencies.
To enable the AD8375, the PWUP pin must be pulled high.
Taking PWUP low puts the AD8375 in sleep mode, reducing
current consumption to 5 mA at ambient.
SINGLE-ENDED-TO-DIFFERENTIAL CONVERSION
The AD8375 can be configured as a single-ended input to
differential output driver as shown in Figure 33. A 150 Ω
resistor in parallel with the input impedance of input pin
provides an impedance matching of 50 Ω. The voltage gain and
the bandwidth of this configuration, using a 150 Ω load,
remains the same as when using a differential input.
5
0.1µF
0.1µF
0.1µF
0.1µF
37.5
150
AD8375
1µH
150
A0 TO A4
1µH
+5V
VCM
0.1µF
50
AC
Figure 33. Single-Ended-to-Differential Conversion
Using a single-ended input decreases the power gain by 3 dB
and limits distortion cancellation. Consequently, the second-
order distortion is degraded. The third-order distortion remains
low to 200 MHz, as shown in Figure 34.
–60
–65
–70
–75
–80
–85
–90
–95
–100
0
200
150
100
50
FREQUENCY (MHz)
HD2
HD3
Figure 34. Harmonic Distortion vs. Frequency of
Single-Ended-to-Differential Conversion
PARALLEL CONTROL INTERFACE
0.1µF
0.1µF
0.1µF
RS
2
RS
2
AC
BALANCED
SOURCE
0.1µF
0.1µF
+VS
RL
BALANCED
LOAD
1µH
1µH
0.1µF
0.1µF
0.1µF
10µF
+VS
COMM VPOS COMM COMM COMM PWUP
19
24
23
22
21
20
A1
A0
VPOS VPOS COMM VPOS
12
78
9
10
11
18
17
16
15
14
13
1
2
3
4
5
6
VCOM
VIN+
VIN–
A4
A3
A2
VOUT–
VOUT+
VOUT–
VOUT+
COMM
VPOS
AD8375
Figure 35. Basic Connections



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