LTC4236 datasheet(13/24 Pages) LINER

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LTC4236

4236f

For more information www.linear.com/LTC4236

applicaTions inForMaTion

Turn-On Sequence

The board power supply at the OUT pin is controlled

with external N-channel MOSFETs (MD1, MD2 and MH) in

Figure 1. The ideal diode MOSFETs connected in parallel

on the supply side function as a diode-OR, while MH on

the load side acts as a Hot Swap MOSFET controlling the

power supplied to the output load. The sense resistor RS

monitors the load current for overcurrent detection. The

HGATE capacitor CHG controls the gate slew rate to limit

the inrush current. Resistor RHG with CHG compensates

the current control loop, while RHpreventshighfrequency

oscillations in the Hot Swap MOSFET.

During a normal power-up, the ideal diode MOSFETs turn

onfirst.Assoonastheinternallygeneratedsupply,INTVCC,

rises above its 2.2V undervoltage lockout threshold, the

internal charge pump is allowed to charge up the CPO

pins. Because the ideal diode MOSFETs are connected in

parallelasadiode-OR,theSENSE+pinvoltageapproaches

the highest of the supplies at the IN1 and IN2 pins. The

MOSFET associated with the lower input supply voltage

willbeturnedoffbythecorrespondinggatedriveamplifier.

Before the Hot Swap MOSFET can be turned on, EN must

remain low and ON must remain high for a debounce cycle

as configured at the DTMR pin, to ensure that any contact

bounces during the insertion have ceased. At the end of

the debounce cycle, the internal fault latch is cleared. The

Hot Swap MOSFET is then allowed to turn on by charging

up HGATE with a 10µA current source from the charge

pump. The voltage at the HGATE pin rises with a slope

equal to 10µA/CHG and the supply inrush current flowing

into the load capacitor CL is limited to:

IINRUSH =

CHG

•10µA

The OUT voltage follows the HGATE voltage when the Hot

Swap MOSFET turns on. If the voltage across the current

sense resistor RS becomes too high based on the FB pin

voltage, the inrush current will be limited by the internal

current limiting circuitry. Once the MOSFET gate overdrive

exceeds 4.2V and the FB pin voltage is above 1.235V, the

PWRGD pin pulls low to indicate that the power is good.

Once OUT reaches the input supply voltage, HGATE con-

tinues to ramp up. An internal 12V clamp limits the HGATE

voltage above OUT.

When the ideal diode MOSFET is turned on, the gate

drive amplifier controls the gate of the MOSFET to servo

the forward voltage drop across the MOSFET to 15mV.

If the load current causes more than 15mV of drop, the

MOSFET gate is driven fully on and the voltage drop is

equal to ILOAD • RDS(ON).

Turn-Off Sequence

The external MOSFETs can be turned off by a variety of

conditions. A normal turn-off for the Hot Swap MOSFET is

initiated by pulling the ON pin below its 1.155V threshold

(80mV ON pin hysteresis), or pulling the EN pin above its

1.235V threshold. Additionally, an overcurrent fault that

exceeds the fault timer period also turns off the Hot Swap

MOSFET. Normally, the LTC4236 turns off the MOSFET by

pulling the HGATE pin to ground with a 2mA current sink.

All of the MOSFETs turn off when INTVCC falls below its

undervoltage lockout threshold (2.2V). The DGATE pin is

pulled down with a 100µA current to one diode voltage

belowtheIN1orD2SRCpins,whiletheHGATEpinispulled

down to the OUT pin by a 200mA current. When D2OFF

is pulled high above 1.235V, the ideal diode MOSFET in

the IN2 power path is turned off with DGATE2 pulled low

by a 100µA current.

The gate drive amplifier controls the ideal diode MOSFET

to prevent reverse current when the input supply falls

below SENSE+. If the input supply collapses quickly, the

gate drive amplifier turns off the ideal diode MOSFET with

a fast pull-down circuit. If the input supply falls at a more

modest rate, the gate drive amplifier controls the MOSFET

to maintain SENSE+ at 15mV below IN.

Board Presence Detect with EN

If ON is high when the EN pin goes low, indicating a board

presence,theLTC4236initiatesatimingcycleasconfigured

at the DTMR pin for contact debounce. It defaults to inter-

nal 100ms delay if DTMR is tied to INTVCC. If an external

capacitor CDT is connected from the DTMR pin to GND,

the delay is given by charging the capacitor to 1.235V with

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