LTC4236 datasheet(20/24 Pages) LINER

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LTC4236

4236f

For more information www.linear.com/LTC4236

applicaTions inForMaTion

It is also important to place the bypass capacitor C1 for

the INTVCC pin, as close as possible between INTVCC and

GND. Also place C2 near the CPO1 and IN1 pins, C3 near

the CPO2 and D2SRC pins, and C4 near the REG and

SENSE+ pins. The transient voltage suppressors Z1 and

Z2, when used, should be mounted close to the LTC4236

using short lead lengths.

Power Prioritizer

Figure 8 shows an application where the IN1 supply is

passed to the output on the basis of priority, rather than

simply allowing the highest voltage to prevail. This is

achieved by connecting a resistive divider from IN1 at the

D2OFF pin to suppress the turn-on of the back-to-back

ideal diode MOSFETs, MD2 and MD3 in the IN2 power path.

In this application, the 5V primary supply (VIN1) is passed

to the output whenever it is available; power is drawn

from the 12V backup supply (VIN2) only when the primary

supply is unavailable. As long as VIN1 is above the 4.7V

threshold set by the R6-R7 divider at the D2OFF pin, MD2

and MD3 are turned off, allowing VIN1 to be connected to

the output through MD1. The common source terminals of

MD2 and MD3 are connected to D2SRC pin, which allows

the body-diode of MD2 to reverse block the current flow

from the higher backup supply (VIN2) to the output. If the

primary supply fails and VIN1 drops below 4.3V, D2OFF is

allowed to turn on MD2 and MD3, and connect the VIN2 to

the output. When VIN1 returns to a viable voltage, MD2 and

MD3 turn off, and the output is connected to VIN1. Adding

R5 in the R6-R7 divider and bypassing it with DSTAT2 pin

control allows the D2OFF pin hysteresis to be increased

from 20mV to 100mV. The resistive divider at the ON pin

sets the SENSE+ undervoltage threshold to 4.1V.

•••

•

••

•

PowerPAK SO-8

MD1

PowerPAK SO-8

MD2

PowerPAK SO-8

IN1

VIA TO IN1

CURRENT FLOW

TO LOAD

OUT

IN2

CURRENT FLOW

TO LOAD

TRACK WIDTH W:

0.03" PER AMPERE

ON 1oz Cu FOIL

VIA TO C2 (CPO1)

VIA TO DGATE2

VIA TO C4 (REG)

VIA TO SENSE+

VIA TO GND PLANE

VIA TO DGATE1

9 10 11 12 13

28 27 26 25 24

LTC4236UFD

4236 F07

Figure 7. Recommended PCB Layout for Power MOSFETs and Sense Resistor

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