MPC755 datasheet(17/56 Pages) MOTOROLA

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MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1

Freescale Semiconductor

Electrical and Thermal Characteristics

Figure 6 provides the input/output timing diagram for the MPC755.

Figure 6. Input/Output Timing Diagram

4.2.3

L2 Clock AC Specifications

The L2CLK frequency is programmed by the L2 configuration register (L2CR[4–6]) core-to-L2 divisor ratio. See

Table 17 for example core and L2 frequencies at various divisors. Table 11 provides the potential range of L2CLK

output AC timing specifications as defined in Figure 7.

The minimum L2CLK frequency of Table 11 is specified by the maximum delay of the internal DLL. The

variable-tap DLL introduces up to a full clock period delay in the L2CLK_OUTA, L2CLK_OUTB, and

L2SYNC_OUT signals so that the returning L2SYNC_IN signal is phase-aligned with the next core clock (divided

by the L2 divisor ratio). Do not choose a core-to-L2 divisor which results in an L2 frequency below this minimum,

or the L2CLK_OUT signals provided for SRAM clocking will not be phase-aligned with the MPC755 core clock at

the SRAMs.

The maximum L2CLK frequency shown in Table 11 is the core frequency divided by one. Very few L2 SRAM

designs will be able to operate in this mode, especially at higher core frequencies. Therefore, most designs will select

a greater core-to-L2 divisor to provide a longer L2CLK period for read and write access to the L2 SRAMs. The

maximum L2CLK frequency for any application of the MPC755 will be a function of the AC timings of the

MPC755, the AC timings for the SRAM, bus loading, and printed-circuit board trace length. The current AC timing

of the MPC755 supports up to 200 MHz with typical, similarly-rated SRAM parts, provided careful design practices

are observed. Clock trace lengths must be matched and all trace lengths should be as short as possible. Higher

frequencies can be achieved by using better performing SRAM. Note that revisions of the MPC755 prior to Rev. 2.8

(Rev. E) were limited in performance, and were typically limited to 175 MHz with similarly-rated SRAM. For more

information, see Section 10.2, “Part Numbers Not Fully Addressed by This Document.”

SYSCLK

All Inputs

All Outputs

tKHOX

(Except TS, ABB,

ARTRY, DBB)

TS, ABB, DBB

ARTRY

tKHOZ

tKHABPZ

tKHARPZ

tKHARP

tKHOV

tKHOX

tKHOV

tKHOX

tKHOV

tIVKH

tIXKH

tKHOZ

tKHOE

VM = Midpoint Voltage (OVDD/2 or Vin/2)

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