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MPC755 数据表(PDF) 2 Page - Motorola, Inc |
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MPC755 数据表(HTML) 2 Page - Motorola, Inc |
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2 / 56 page ![]() MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1 2 Freescale Semiconductor Overview 1 Overview The MPC755 is targeted for low-cost, low-power systems and supports the following power management features—doze, nap, sleep, and dynamic power management. The MPC755 consists of a processor core and an internal L2 tag combined with a dedicated L2 cache interface and a 60x bus. The MPC745 is identical to the MPC755 except it does not support the L2 cache interface. Figure 1 shows a block diagram of the MPC755. |
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