AC207-DS02-R datasheet(12/60 Pages) BOARDCOM

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AC207

Preliminary Data Sheet

07/08/02

B roa dcom

Page 2

Transceiver and Transmit Function

Document

AC207-DS04-405-R

SCRAMBLER

In 100BASE-TX mode, the internal 5-bit transmit data stream is scrambled as defined by the TP-PMD Stream Cipher

function in order to reduce radiated emissions on the twisted pair cable. The scrambler encodes a plain text NRZ bit stream

using a key stream periodic sequence of 2047 bits generated by the recursive linear function:

X [n] = X [n-11] + X [n-9] (modulo 2)

The scrambler reduces peak emissions by randomly spreading the signal energy over the transmit frequency range, thus

eliminating peaks at a single frequency. EMI emission can be further reduced by assigning a unique scrambled seed to each

port. When the BT Control register 23.11 is set to 1 the data scrambling function is disabled, the 5-bit data stream is clocked

directly to the device’s PMA sublayer.

PARALLEL TO SERIAL AND NRZ – NRZI TO MLT-3 CONVERSION

The internal 5-bit NRZ data is clocked into Transceiver’s shift register with a 25-MHz clock, and clocked out with a 125-MHz

clock to convert it into a serial bit stream. Both clocks are generated by an on-chip clock synthesizer, and they are in sync

to each other. The serialized data is further converted from NRZ to NRZI format, which produces a transition on every logic

1 and no transition on logic 0. To further reduce EMI emission, the NRZI data is converted to MLT-3 signal. The effect offers

a 3 dB to 6 dB reduction in EMI emissions over an un-converted NRZI signals, thus increases the output signals’ margin of

operating within the FCC Class B limit.

When there is a transition occurring in NRZI data, there is a corresponding transition for MLT-3 data. For NRZI data, it

changes the count up/down direction after every single transition. For MLT-3 data, it changes the count up/down direction

after every two transitions. The NRZI to MLT-3 data conversion is implemented without reference to the bit timing or clock

information. The conversion requires detecting transition of the incoming NRZI data and set up the count up/down direction

for the MLT-3 data. Asserting FX_SEL high bypasses this encoding.

MULTIMODE TRANSMIT DRIVER

The multimode driver transmits MLT-3 coded signal in 100BASE-TX mode and Manchester coded signal in 10BASE-T

mode.

The slew rate of the transmitted MLT-3 signal can be controlled to eliminate high frequency EMI component. The MLT-3

signal after the magnetic has a typical rise/fall time of approximately 4 ns, which is within the target range specified in the

ANSI TP- PMD standard.

In 10BASE-T mode, high frequency pre-emphasis is performed which extends the cable-driving distance without the need

of an external filter. FLP/NLP also drive out through the 10BASE-T driver. The 10BASE-T and 100BASE-TX transmit signals

are multiplexed to the transmit output driver. This arrangement results in using the same external transformer for both the

10BASE-T and the 100BASE-TX. The driver output level is set by a built-in bandgap reference and an external resistor

connected to the RIBB output pin. The resistor sets the output current for all modes of operation. Each of the TXOP/N outputs

is an open drain device which has a source resistance of 10

Ω maximum and a current rating of 40 mA for the 2 Vp-p MLT-

3 signal, 100 mA for 5Vp-p Manchester signal when used 1:1 transformer.

PLL CLOCK SYNTHESIZER

The Transceiver also includes on-chip PLL clock synthesizer that generates a 125-MHz and a 25-MHz clock for the

100BASE-TX or a 100-MHz and 20-MHz clock for the 10BASE-T and auto-negotiation operations. The PLL clock generator

uses a fully differential VCO cell that induces a very low jitter. The Zero Dead Zone Phase Detection method implemented

in this design provides excellent phase tracking. A charge pump with charge sharing compensation is also included to further

reduce jitter at different loop filter voltages. On-chip loop filter eliminates the need for external components and avoids

external noise pickup. Only one external 25-MHz crystal or a signal source is required as a reference clock.

AC207-DS02-R 数据表(PDF) 12 Page - Broadcom Corporation.

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