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AC207-DS02-R 数据表(PDF) 14 Page - Broadcom Corporation.

部件名 AC207-DS02-R
功能描述  2.5V 10/100-TX 8-Port Repeater with Integrated Bridge
PDF  60 Pages
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制造商  BOARDCOM [Broadcom Corporation.]
网页  http://www.broadcom.com
标志 BOARDCOM - Broadcom Corporation.

AC207-DS02-R 数据表(HTML) 14 Page - Broadcom Corporation.

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AC207
Preliminary Data Sheet
07/08/02
B roa dcom
Page 4
Auto-Negotiation and Miscellaneous Functions
Document
AC207-DS04-405-R
CLOCK/DATA RECOVERY
The equalized MLT-3 signal passes through a slicer circuit that converts to NRZI format. The transceiver uses a mixed-signal
phase locked loop (PLL) to extract clock information of the incoming NRZI data. The extracted clock is used to re-time the
data stream and set the data boundaries. The transmit clock is locked to the 25-MHz clock input while the receive clock is
locked to the incoming data streams. When initial lock is achieved, the PLL switches to lock to the data stream, extracts a
125-MHz clock and uses that for bit framing to recover data. The recovered 125-MHz clock is also used to generate an
internal 25-MHz RX_CLK. The PLL requires no external components for its operation and has high noise immunity and low
jitter. It provides fast phase align (lock) to data in one transition and its data/clock acquisition time after power-on is less than
60 transitions. The PLL can maintain lock on run-lengths of up to 60 data bits in the absence of signal transitions. When no
valid data is present, i.e. when the SD is de-asserted, the PLL switches back to lock with TX_CLK, and provides a
continuously running RX_CLK.
DECODER/DESCRAMBLER
The descrambler detects the state of the transmit Linear Feedback Shift Register (LFSR) by looking for a sequence
representing consecutive idle codes. The descrambler acquires lock with the data stream by recognizing IDLE bursts of 30
or more bits and locking to its de-ciphering Linear Feedback Shift Register (LFSR).
Once lock is acquired, the device operates with the inter-packet-gap (IPG) as low as 40 ns. Before lock occurs, the de-
scrambler requires a minimum of 720 nS of idle in between packet in order to acquire lock.
The deciphering logic also tracks the number of consecutive receive errors detected while RX_DV is asserted. Once the
error counter exceeds its limit (currently set to 64 consecutive errors), the logic assumes that lock has been lost, and the de-
cipher circuit resets itself. The process of regaining lock begins again.
Stream cipher de-scrambler is not used in 10BASE-T mode.
AUTO-NEGOTIATION AND MISCELLANEOUS FUNCTIONS
Each of the Transceiver contains the ability to negotiate its mode of operation over the twisted pair using the auto-negotiation
mechanism defined in the clause 28 IEEE 802.3u specification. Auto-negotiation may be disabled by software via EEPROM.
The Transceiver automatically chooses its mode of operation by detecting the incoming signal.
During auto-negotiation, the auto-negotiation advertisement register is sent to its link partner through a series of fast link
pulse (FLP). When auto-negotiation enabled, transceiver sends FLP during the following conditions: a) power-on, b) link
loss, and c) restart command. At the same time, the device monitors incoming data to determine its mode of operation.
Parallel detection circuit is enabled as soon as 10BASE-T idle or 100BASE-TX idle is detected. The mode of operation is
configured based on the technology of the incoming signal. When the device receives a burst of FLP from its link partner
with 3 identical link code words (ignoring acknowledge bit), it stores these code words in the auto-negotiation link partner
ability register and waits for the next 3 identical code word. Once the device detects the second code word, it configures
itself to the highest technology that is common to both ends. The technology priorities are 1) 100BASE-TX, half-duplex, 2)
10BASE-T half-duplex. Once auto-negotiation is complete, the status register reflects the actual speed that was chosen.
PARALLEL DETECTION
The Transceiver also checks for 10BASE-T NLP or 100BASE-TX idle symbols. If either is detected, the device automatically
configures to match the detected operating speed in half-duplex mode. This ability allows the device to communicate with
legacy 10BASE-T and 100BASE-TX systems.



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