AM29BDS640G datasheet(12/65 Pages) SPANSION

12 / 65 page

Am29BDS640G

25903C1 October 1, 2003

Prelimin ary

Input/Output Descriptions

A21-A0

Address inputs

DQ15-DQ0

Data input/output

CE#

Chip Enable input. Asynchronous relative to CLK for

the Burst mode.

OE#

Output Enable input. Asynchronous relative to CLK

for the Burst mode.

WE#

Write Enable input.

VCC

Device Power Supply

(1.65 – 1.95 V).

VIO

Input & Output Buffer Power Supply (either 1.65 –

1.95 V or 2.7 – 3.15 V).

VSS

Ground

VSSIO

Output Buffer Ground

No Connect; not connected internally

RDY

Ready output; indicates the status of the Burst read.

Low = data not valid at expected time. High = data

valid.

CLK

CLK is not required in asynchronous mode. In burst

mode, after the initial word is output, subsequent

active edges of CLK increment the internal address

counter.

AVD#

Address Valid input. Indicates to device that the valid

address is present on the address inputs (A21–A0).

Low = for asynchronous mode, indicates valid

address; for burst mode, causes starting address to

be latched.

High = device ignores address inputs

RESET#

Hardware reset input. Low = device resets and

returns to reading array data

WP#

Hardware write protect input. At VIL, disables

program and erase functions in the two outermost

sectors. Should be at VIH for all other conditions.

ACC

At VID, accelerates programming; automatically

places device in unlock bypass mode. At VIL, locks all

sectors. Should be at VIH for all other conditions.

Logic Symbol

DQ15–DQ0

A21–A0

CE#

OE#

WE#

RESET#

CLK

RDY

AVD#

WP#

ACC

AM29BDS640G 数据表(PDF) 12 Page - SPANSION

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