AM29BDS640G datasheet(14/65 Pages) SPANSION

14 / 65 page

Am29BDS640G

25903C1 October 1, 2003

Prelimin ary

Device Bus Operations

This section describes the requirements and use of the device bus operations,

which are initiated through the internal command register. The command register

itself does not occupy any addressable memory location. The register is com-

posed of latches that store the commands, along with the address and data

information needed to execute the command. The contents of the register serve

as inputs to the internal state machine. The state machine outputs dictate the

function of the device. Table 1 lists the device bus operations, the inputs and con-

trol levels they require, and the resulting output. The following subsections

describe each of these operations in further detail.

Table 1. Device Bus Operations

Legend: L = Logic 0, H = Logic 1, X = Don’t Care, S = Stable Logic 0 or 1 but no transitions.

Note: Default active edge of CLK is the rising edge.

Enhanced VersatileIO™ (VIO) Control

The Enhanced VersatileIO (VIO) control allows the host system to set the voltage

levels that the device generates at its data outputs and the voltages tolerated at

its data and address inputs to the same voltage level that is asserted on the VIO

pin. The device is available with either 1.65–1.95 or 2.7–3.15 VIO. This allows the

device to operate in 1.8 V or 3 V system environments as required.

For example, a VIO of 2.7 – 3.15 volts allows for I/O at the 3 volt level, driving

and receiving signals to and from other 3 V devices on the same bus.

Requirements for Asynchronous Read

Operation (Non-Burst)

To read data from the memory array, the system must first assert a valid address

on A21–A0, while driving AVD# and CE# to VIL. WE# should remain at VIH. The

rising edge of AVD# latches the address. The data will appear on DQ15–DQ0.

Operation

CE#

OE#

WE#

A21–0

DQ15–0

RESET#

CLK

(See

Note) AVD#

Asynchronous Read - Addresses Latched

Addr In

I/O

Asynchronous Read - Addresses Steady State

Addr In

I/O

Asynchronous Write

Addr In

I/O

Synchronous Write

Addr In

I/O

Standby (CE#)

HIGH Z

Hardware Reset

HIGH Z

Burst Read Operations

Load Starting Burst Address

Addr In

Advance Burst to next address with

appropriate Data presented on the Data Bus

HIGH Z

Burst

Data Out

Terminate current Burst read cycle

HIGH Z

Terminate current Burst read cycle via RESET#

HIGH Z

Terminate current Burst read cycle and start

new Burst read cycle

HIGH Z

I/O

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