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ADL5519ACPZ-R7 数据表(PDF) 28 Page - Analog Devices

部件名 ADL5519ACPZ-R7
功能描述  1 MHz to 10 GHz, 62 dB Dual Log Detector/Controller
PDF  39 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADL5519ACPZ-R7 数据表(HTML) 28 Page - Analog Devices

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ADL5519
Data Sheet
Rev. B | Page 28 of 39
APPLICATIONS INFORMATION
MEASUREMENT MODE
The ADL5519 is placed in measurement mode by connecting
OUTA, OUTB to VSTA, VSTB, respectively. The part has an offset
voltage, a negative slope, and a VOUTA, VOUTB measurement inter-
cept at the high end of its input signal range.
The output voltage vs. input signal voltage of the ADL5519 is
linear-in-dB over a multidecade range. The equation for this
function is of the following form:
VOUT = x × VSLOPE/DEC × log10(VIN/VINTERCEPT) =
(13)
x × VSLOPE/dB × 20 × log10(VIN/VINTERCEPT)
(14)
where:
x is the feedback factor in VSET = VOUT/x.
VSLOPE/DEC is nominally −440 mV/decade or −22 mV/dB.
VINTERCEPT is the x-axis intercept of the linear-in-dB portion of
the VOUT vs. VIN curve.
VINTERCEPT is 2 dBV for a sinusoidal input signal.
An offset voltage, VOFFSET, of 0.45 V is internally added to
the detector signal so that the minimum value for VOUT is
x × VOFFSET. If x = 1, the minimum VOUT value is 0.45 V.
The slope is very stable vs. process and temperature variation.
When Base-10 logarithms are used, VSLOPE/DEC represents the
volts/decade. A decade corresponds to 20 dB; VSLOPE/DEC/20 =
VSLOPE/dB represents the slope in V/dB.
As noted in Equation 13 and Equation 14, the VOUT voltage has
a negative slope. This is also the correct slope polarity to control
the gain of many VGAs in a negative feedback configuration.
Because both the slope and intercept vary slightly with frequency,
see the Specifications section for application-specific values for
slope and intercept.
Although demodulating log amps respond to input signal
voltage and not input signal power, it is customary to discuss
the amplitude of high frequency signals in terms of power. In
this case, the characteristic impedance of the system, Z0, must
be known to convert voltages to their corresponding power levels.
The following equations are used to perform this conversion:
P (dBm) = 10 × log10(Vrms2/(Z0 × 1 mW))
(15)
P (dBV) = 20 × log10(Vrms/1 Vrms)
(16)
P (dBm) = P (dBV) − 10 × log10(Z0 × 1 mW/1 Vrms2)
(17)
For example, PINTERCEPT, for a sinusoidal input signal expressed
in terms of dBm (decibels referred to 1 mW), in a 50 Ω system is
PINTERCEPT (dBm) =
PINTERCEPT (dBV) − 10 × log10(Z0 × 1 mW/1 Vrms2) =
2 dBV − 10 × log10(50 × 10−3) = 15 dBm
For a square wave input signal in a 200 Ω system
PINTERCEPT (dBm) =
−1 dBV − 10 × log10[(200 Ω × 1 mW/1Vrms2)] = +6 dBm
More information about the intercept variation dependence upon
waveform can be found in the AD8313 and AD8307 data sheets.
As the input signals to Channel A and Channel B are swept over
their nominal input dynamic range of −5 dBm to −55 dBm, the
output swings from 0.5 V to 1.6 V. The voltages of OUTA, OUTB
are also internally applied to a difference amplifier with a gain
of 1. When the input power is swept, OUTP swings from approxi-
mately 0.5 V to 1.75 V, and OUTN swings from 1.75 V to 0.5 V.
The VLVL pin sets the common-mode voltage for OUTP, OUTN.
An output common-mode voltage of ≤1.15 V can be set using
a resistor divider between the VREF and VLVL pins. Measurement
of large differences between INHA, INHB can be affected by
on-chip signal leakage.
CONTROLLER MODE
In addition to being a measurement device, the ADL5519 can
also be configured to set and control signal levels. Each of the two
log detectors can be separately configured to set and control the
output power level of a VGA or variable voltage attenuator (VVA).
See the Controller Mode section of the AD8317 datasheet for more
information on running a single channel in controller mode.
Alternatively, the two log detectors can be configured to measure
and control the gain of an amplifier or signal chain. The channel
difference outputs can be used to control a feedback loop to the
ADL5519 RF inputs. A capacitor connected between FBKA and
OUTP forms an integrator, keeping in mind that the on-chip 1 kΩ
feedback resistor forms a 0. (The value of the on-chip resistors can
vary as much as ±20% with manufacturing process variation.)
If Channel A is driven and Channel B has a feedback loop from
OUTP through a VGA, OUTP integrates to a voltage value
such that
OUTB = (OUTA + VLVL)/2
(18)
The output value from OUTN may or may not be useful. It is
given by
OUTN = 0 V
(19)
for VLVL < OUTA/3.
Otherwise,
OUTN = (3 × VLVL − OUTA)/2
(20)



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